Table of Contents |
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Introduction
This page gives an overview of qspipsu driver which is available as part of the Xilinx Vivado and Vitis distribution.Source path for the driver:
Table of Contents |
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Introduction
The quad SPI (QSPI) controller can access one or two flash devices using several different methods. The controller is located with the other flash memory controllers in the PMC. The I/Ointerface is routed to the PMC MIO pin bank 0 and can drive one or two devices. QSPI is commonly used as a boot device.
• SPI accesses
• Programmed I/O (PIO) protocol
• DMA indirect read using AXI master interface
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
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qspipsu | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/qspipsu | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/qspipsu |
Info |
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Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/ |
The driver source code is organized into different folders.
The table below shows the qspipsu driver source organization.
Directory | Description |
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doc |
Provides the API and data structure details |
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- Examples - Reference application to
data | Driver .tcl and .mdd file |
examples | Example applications that show how to use the driver |
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- Source -
features | |
src | Driver source files |
Features Supported
The controller driver will be exclusive to GQSPI including API’s to be used for configuring the host controller and transmitting the data.Commands Supported:
The following list of basic commands are supported by the Standalone driver:Controller Features Supported:
The following features are supported in the QSPI Standalone driver.2016.3
- Added Tap delay support
- Added example support for LQSPI
- Added PollData and PollTimeout Support
2016.4
- Update GQSPI PollData/PollTimeout for dualparallel configurations
2017.1
- None
2017.2
- None
2017.3
- Added support for accessing upper DDR
- Added CCI support
2017.4
- Replaced the #ifdef COMMENTS with #if USE_FOUR_BYTE
- Examples made compatible with u-boot and linux.
- Resolved errors in qspipsu for ICCARM compiler
- lqspi and poll data poll timeout example made compatible with u-boot and linux.
2018.1
- Removed unsupported 4 byte commands.
- Added support for MT25QL02G, S25FL064L and MX66U1G45G flash parts.
- Removed check before writing destination address to DMA MSB.
- Added a support to toggle WP pin of the flash.
- Added support in EL1 NS mode.
- Enable both CS in dual parallel mode, when issuing Write enable command.
2018.2
- None
2018.3
2019.1
2019.2
2020.1
2020.2
- Update Makefile for parallel make execution
Driver Implementation
For a full list of features supported by this IP, please refer Chapter 71: Quad SPI Controller in Versal TRM
Features
- DMA access (aligned address only)
- IO access
- Control of two chip selects/bus
- Configurable clock
- Configurable bus width
- Byte Mirror/Stripe operations
- Interrupts – will be chosen and enabled internally
Example Applications:
- Generic register read/write operations
- 3 byte and 4 byte addressing
- Flash configurations illustrated in examples – Single, Dual Stacked, Dual Parallel
Known issues and Limitations
The standalone driver supports GenericQSPI(GQSPI) not Linear QSPI(LQSPI)Test cases
Sample output of test cases that are taken from examples folder specified aboveQSPIPSU FLASH Interrupt Example Test Successfully ran QSPIPSU FLASH Interrupt Example Test |
QSPIPSU FLASH Polling Example Test Successfully ran QSPIPSU FLASH Polling Example Test |
Performance Details
Single
Qspipsu write throughput is 1326 KBPSQspipsu read throughput is 28339 KBPS
Dual-Parallel
Qspipsu write throughput is 2438 KBPSQspipsu read throughput is 54245 KBPS
Change Log
- SPI NAND flash devices
Known Issues and Limitations
Supported Flash vendors
- Micron
- ISSI
- Spansion
- Macronix
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/qspipsu/examples
Test Name | Example source | Description |
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Generic QSPI Interrupt Mode Example | This examples does basic read and write test from the SPI-NOR flash device in Interrupt mode. | |
Generic QSPI Polled Mode Example | This examples does basic read and write test from the SPI-NOR flash device in Polled mode. | |
Generic QSPI Non-blocking read example | This examples does read in non blocking polled mode from the SPI-NOR flash device. | |
Generic QSPI NAND Interrupt Mode Example | This examples does basic read and write test from the SPI-NAND flash device in Interrupt mode. | |
Generic QSPI NAND Polled Mode Example | This examples does basic read and write test from the SPI-NAND flash device in Polled mode. | |
Generic QSPI 64 Bit DMA Mode Example | This example does read in polled mode with 64bit DMA from SPI-NOR flash device. | |
Generic QSPI Write Protection Example | This example tests the write protection feature of the SPI-NOR flash device | |
Generic QSPI Polldata Mode Example | This example illustrates, the use of polldata feature of the controller | |
Linear QSPI Example | This example writes in GQSPI mode & reads in linear mode. |
Example Application Usage
Generic QSPI Interrupt Mode Example
This examples does basic read and write test from the flash device in Interrupt mode.
Expected Output
QSPIPSU Generic Flash Interrupt Example Test
Cfg Init done, Baseaddress: 0xF1030100
FlashID=0x20 0xBB 0x21
Flash connection mode : 2
where 0 - Single; 1 - Stacked; 2 - Parallel
FCTIndex: 10
ReadCmd: 0x6B, WriteCmd: 0x2,StatusCmd: 0x70, FSRFlag: 1
Successfully ran QSPIPSU Generic Interrupt Example |
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Generic QSPI Polled Mode Example
This examples does basic read and write test from the flash device in Polled mode.
Expected Output
QSPIPSU Generic Flash Polled Example Test
FlashID=0x20 0xBB 0x21
Flash connection mode : 2
where 0 - Single; 1 - Stacked; 2 - Parallel
FCTIndex: 10
ReadCmd: 0x6B, WriteCmd: 0x2, StatusCmd: 0x70, FSRFlag: 1
Successfully ran QSPIPSU Generic Flash Polled Example |
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Generic QSPI 64 Bit DMA Mode Example
This example does read in polled mode with 64bit DMA.
Expected Output
QSPIPSU Generic Flash Polled Example 64bit dma for r5Test
FlashID=0x20 0xBB 0x21
Flash connection mode : 2
where 0 - Single; 1 - Stacked; 2 - Parallel
FCTIndex: 10
ReadCmd: 0x6B, WriteCmd: 0x2, StatusCmd: 0x70,FSRFlag: 1
Successfully ran Generic Flash Polled 64 bit dma r5 Example |
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Generic QSPI Polldata Mode Example
This example illustrates, the use of polldata feature of the controller
Expected Output
QSPIPSU Flash PollData and PollTimeout Example Test
Cfg Init done, Baseaddress: 0xF1030100
FlashID=0x20 0xBB 0x21
Flash connection mode : 2
where 0 - Single; 1 - Stacked; 2 - Parallel
FCTIndex: 10
ReadCmd: 0x6B, WriteCmd: 0x2, StatusCmd: 0x70, FSRFlag: 1
Successfully ran QSPIPSU PollData and PollTimeout Example |
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Generic QSPI Non-blocking read Example
This examples does read in non blocking polled mode from the SPI-NOR flash device.
Expected Output
QSPIPSU Generic Flash Non Blocking Read Example Test
FlashID=0x20 0xBB 0x21
Flash connection mode : 2
where 0 - Single; 1 - Stacked; 2 - Parallel
FCTIndex: 10
ReadCmd: 0x6B, WriteCmd: 0x2, StatusCmd: 0x70, FSRFlag: 1
Successfully ran QSPIPSU Generic Flash Non Blocking Read Example |
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Generic QSPI Write Protection Example
This example tests the write protection feature of the SPI-NOR flash device
Expected Output
QSPIPSU Write Protect Example Test
Cfg Init done, Baseaddress: 0xF1030100
FlashID=0x20 0xBB 0x21
Flash connection mode : 2
where 0 - Single; 1 - Stacked; 2 - Parallel
FCTIndex: 10
ReadCmd: 0xB, WriteCmd: 0x2, StatusCmd: 0x70, FSRFlag: 1
Successfully ran QSPIPSU Write Protect Example |
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Example Design Architecture
NA
Performance
Single
Qspipsu write throughput is 1326 KBPS
Qspipsu read throughput is 28339 KBPS
Dual-Parallel
Qspipsu write throughput is 2438 KBPS
Qspipsu read throughput is 54245 KBPS
Change Log
2021.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L374
2020.2
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L653
2020.1
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L95
2019.2
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.2/doc/ChangeLog#L70
2019.1
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.1/doc/ChangeLog#L132