Introduction

This page gives an overview of nandpsu driver which is available as part of the Xilinx Vivado and SDK distribution.
Source path for the driver:

The NAND flash controller configuration and operational registers are programmed via its AXI slave interface. The block supports the open NAND flash interface working group (ONFI) standards 1.0, 2.0, 2.1, 2.2, 2.3, 3.0, and 3.1. The controller handles all the command, address, and data sequences, manages all the hardware protocols, and allows access NAND flash memory simply by reading or writing into the operational registers. The NAND DMA controller accesses system memory using its AXI master interface.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Driver Name	Path in Vitis	Path in Github
nandpsu	<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/nandpsu	https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/nandpsu

Info
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/

master

xilinx-v2020.1/XilinxProcessorIPLib/drivers/nandpsu

Driver

The driver source code is organized into different folders.

Below diagram

The table below shows the

nandpsu driver

nandpsudriver source organization.

Directory

nandpsu

Description

|

doc

-- Doc -

Provides the API and data structure details

|
- Examples - Reference application to


data	Driver .tcl and .mdd file
examples	Example applications that show how to use the driver

APIs and calling sequence
|
- Source - Controller Features:

features
src	Driver source files

Features Supported

Driver Implementation

For a full list of features supported by this IP, please refer Chapter 25: NAND Memory Controller in ZynqMP TRM.

Features

Complies with the ONFI 3.1 specification
Supports interleaving operations
Supports BCH error correction code (ECC) data widths of 4, 8, 12, and 24 bits.
All ONFI 3.1 commands
PIO and MDMA support
SDR

and NVDDR modes

mode
supports only 8-bit bus support
Hardware ECC (Hamming code and BCH)
Page size up to 16K
Programmable timing modes
64-bit dma support.
Supports multiple chip selects (up to 2)

Known Issues and Limitations

Driver

Features:Supports only the mandatory

supports polled mode only
No support for interleaved and all optional ONFI 3.1 commands

. i.e Reset, Read status, Read ID, Read Parameter Page, Read Page, Program Page, Erase Block, Set/Get Features

Supports SDR/DDR modes

Supports timing modes 0-5

Supports PIO and MDMA support

Support for multiple chip selection

Support BBT management

Bad Block management

Bad block management implementation is same as Linux MTD bad block management with the exception of reserving number of blocks to store Bad Block Table (BBT) from default 4 blocks to 64 blocks. This is because one of the Micron flash part MT29F32G08ABCDB has last 32 blocks as bad most of the times. Since it was difficult to store bad block table in last 4 blocks, the number of blocks are increased to 64 blocks.

Supported Flash vendors

Micron

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab

Links to Examples

Examples Path:

https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/nandpsu/examples

Test Name	Example Souce	Description
NAND Example	xnandpsu_example.c	This examples does basic read and write test from the NAND flash device

Example Application Usage

NANDP Example

This examples does basic read and write test from the NAND flash device.

Nand Flash Read Write Example Test

Manufacturer: MICRON      MT29F32G08ABCDBJ4   ,

Device Model: MT29F32G08ABCDBJ4   ,

Jedec ID: 0x2C

Bytes Per Page: 0x4000

Spare Bytes Per Page: 0x4C0

Pages Per Block: 0x100

Blocks Per LUN: 0x418

Number of LUNs: 0x1

Number of bits per cell: 0x1

Number of ECC bits: 0xFF

Block Size: 0x400000

Number of Target Blocks: 0x418

Number of Target Pages: 0x41800

ECC: addr 0x4220 size 0x2A0 numbits 24 codesz 10

XNandPsu_ReadBbt: Bad block table not found

Successfully ran Nand Flash Read Write Example Test

Example Design Architecture

NA

Performance

SDR Mode 5 write throughput is 15784 KBP
SDR Mode 5 read throughput is 24526 KBPS

Change Log

2021.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L455

2020.2

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L637

2020.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L6

2019.2

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.2/doc/ChangeLog#L801

2019.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.1/doc/ChangeLog#L562

Known issues and Limitations

Driver supports polled mode only
No support for interleaved and all optional ONFI 3.1 commands

ChangeLog

2016.3
- Summary
  - None
- Commits
  - None
2016.4
- Summary
  - None
- Commits
  - None
2017.1
- Summary
  - Fix for reading nand redundant parameter pages
- Commit id
  - a6b32ee
2017.2
- Summary
  - None
- Commits
  - None
2017.3
- Summary
  - Added CCI support
- Commit
  - cdd0434
2017.4
- Summary
  - None
- Commits
  - None
2018.1
- Summary
  - None
- Commits
  - None
2018.2
- Summary
  - None
- Commits
  - None
2018.3
- Summary
  - Support 64 bit DMA addresses for Microblaze-X
- Commit
  - b87f96d
2019.1
- Summary
  - None
- Commits
  - None
2019.2
- Summary
  - None
- Commits
  - None
2020.1
- Summary
  - Add clocking support
- Commits
  - 62f0890
2020.2
- Summary
  - None
- Commits
  - None

Test cases

Nandpsu example:

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/nandpsu/examples/xnandpsu_example.c
It verifies the nand data integrity by programing the known data pattern and verify the same by reading the data back.
In this process erase, program, read, read ID, Read Parameter Page, Reset, read status, get/set features and bbt management are covered
Output:

Code Block

theme	Midnight

Xilinx Zynq MP First Stage Boot Loader 

Release 2020.1   May 24 2020  -  13:51:37
Nand Flash Read Write Example Test
Manufacturer: MICRON      MT29F32G08ABCDBJ4   ,
Device Model: MT29F32G08ABCDBJ4   ,
Jedec ID: 0x2C
Bytes Per Page: 0x4000
Spare Bytes Per Page: 0x4C0
Pages Per Block: 0x100
Blocks Per LUN: 0x418
Number of LUNs: 0x1
Number of bits per cell: 0x1
Number of ECC bits: 0xFF
Block Size: 0x400000
Number of Target Blocks: 0x418
Number of Target Pages: 0x41800
ECC: addr 0x4220 size 0x2A0 numbits 24 codesz 10
XNandPsu_ReadBbt: Bad block table found
Successfully ran Nand Flash Read Write Example Test

Performance:

Timing Mode	Write(MBPS)	Read(MBPS)
SDR mode 0	6.4	7.7
SDR mode 1	11.2	15.1
SDR mode 2	13.0	18.7
SDR mode 3	15.1	24.4
SDR mode 4	15.6	24.5
SDR mode 5	15.7	24.5
NVDDR mode 0	31.0	107.7
NVDDR mode 1	31.0	106.2
NVDDR mode 2	31.0	106.3
NVDDR mode 3	31.0	107
NVDDR mode 4	31.0	106.3
NVDDR mode 5	31.0	106.3

Page Comparison

Versions Compared

Old Version 11

New Version 12

Key

Table of Contents

Introduction

Driver Sources

Features Supported

Driver Implementation

Features

Known Issues and Limitations

Bad Block management

Supported Flash vendors

Example Applications

Links to Examples

Example Application Usage

NANDP Example

Example Design Architecture

Performance

Change Log

2021.1

2020.2

2020.1

2019.2

2019.1

Related Links

Known issues and Limitations

ChangeLog

2016.3

2016.4

2017.1

2017.2

2017.3

2017.4

2018.1

2018.2

2018.3

2019.1

2019.2

2020.1

2020.2

Test cases

Nandpsu example:

Performance:

Related Links