LLFIFO Standalone Driver
Table of Contents
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Introduction
This page gives an overview of the llfifo driver which is available as part of the Xilinx Vivado and SDK distribution.
Table of Contents
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Introduction
The LogiCORE™ IP AXI4-Stream FIFO core allows memory mapped access to an AXI4-Stream interface.
The core can be used to interface to AXI Streaming IPs, Similar to the LogiCORE IP AXI Ethernet core,
Without having to use a full DMA solution. The principal operation of this core allows the write or read
Of data packets to or from a device without any concern over the AXI4-Stream interface signaling.
You can easily manage the AXI4-Stream interfaces as they are transparent.
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| Directory | Description |
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doc | Provides the API and data structure details |
data | Driver .tcl , .mdd and .mdd fileyaml files |
examples | Example applications that show how to use the driver features |
| src | Driver source files, make and cmakelists file |
Driver Implementation
For a full list of features supported by this IP, please refer TRM
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Example Application Usage
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llfifo Polled mode example
This example is the polling example for the FIFO it assumes that at the h/w level FIFO is connected in
Loopback. In these we write a known amount of data to the FIFO and Receive the data and compare with the data transmitted.
Expected Output
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