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Introduction
This page gives an overview of AXI-I2C driver which is available as part of the Xilinx Vivado and SDK distribution.
The LogiCORE™ IP AXI IIC Bus Interface connects to the AMBA® AXI specification and provides a low-speed, two-wire,
serial bus interface to a large number of popular devices. This product specification defines the architecture,
hardware (signal) interface, software (register) interface, and parameterization options for the AXI IIC Bus Interface module.
Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/iic
Driver source code is organized into different folders. Below diagram shows the iicps driver source organization
Axi-iic
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-- Doc - Provides the API and data structure details
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- Examples - Reference application to show how to use the driver APIs and calling sequence
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- Source - Driver source files
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
| Driver Name | Path in Vitis | Path in Github |
|---|---|---|
| iic | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/iic | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/iic |
| Info |
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Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/iic |
Controller Features Supported:
• Register access through AXI4-Lite interface• Master or slave operation
• Multi-master operation
• Software selectable acknowledge bit
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt with automatic mode switching from master to slave
• START and STOP signal generation and detection
• Repeated START signal generation
• Acknowledge bit generation and detection
• Bus busy detection
• Fast-Mode Plus 1 MHz, Fast Mode 400 kHz, or Standard Mode 100 kHz operation
• 7-bit or 10-bit addressing
• General call enable or disable
• Transmit and receive FIFOs – 16 bytes deep
• Throttling
• General purpose output, 1-bit to 8 bits wide
• Dynamic Start and Stop generation
Driver Supported Features
- The axi-iic Standalone driver support the below things.
- All Controller Features supported.
Known issues and Limitations
- None.
Test cases
Refer below pah for testing different examples for each feature of the IP.https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/iic/examples
ChangeLog
- 2017.1
- Added xil_printf statement in examples.
- Updated Makefile.
- Added readme.txt file to generate doxygen for examples.
- 2017.2
- Modified comment lines notation of functions
- Changed modification history in examples
- 2017.3
- None
- 2017.4
- None
- 2018.1
- None
- 2018.2
- updated copyright for iic
- 2018.3
- iic: Update the fifo flush
- iic: Update the bus wait for the nack caseFixes the bus busy check in case of nack
- 2019.1
- drivers: Changes in Makefile to make map file consistent in windows and linux
- 2019.2
- None
- 2020.1
- Summary
- drivers: Fix makefiles issue for windows
- Commits
- Summary
- 2020.2
- Summary
- drivers: iic: Add conditional flushing of RxFIFO
- Commits
- Summary