Table of Contents
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Overview
This documents provides driver details about the Synopsys DDR ECC controller driver used in Zynq and ZynqMP SOC.HW/IP Features
Zynq DDRC controller and ZynqMP SOC DDRC Controller supports single bit error correction and double bit error detectionZynqMP DDRC controller has interrupt support and error injection support.
Zynq DDRC controller reports the single and double bit errors based on poll method.
ZynqMP DDRC controller reports the single and double bit errors based on interrupt method.
Missing features, Known Issues and Limitations
- None
Kernel Configurations
The following kernel configuration options should be enabled for compiling the Synopsys EDAC driver
CONFIG_EDAC_SYNOPSYS = y
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CONFIG_EDAC_SYNOPSYS: │ │ │ │ Support for error detection and correction on the Synopsys DDR │ │ memory controller. │ │ │ │ Symbol: EDAC_SYNOPSYS [=m] │ │ Type : tristate │ │ Prompt: Synopsys DDR Memory Controller │ │ Location: │ │ -> Device Drivers │ │ -> EDAC (Error Detection And Correction) reporting (EDAC [=y]) │ │ -> Main Memory EDAC (Error Detection And Correction) reporting (EDAC_MM_EDAC [=y]) │ │ Defined at drivers/edac/Kconfig:386 │ │ Depends on: EDAC [=y] &&&& EDAC_MM_EDAC [=y] &&&& (ARM [=y] || ARM64) |
Device tree Node Settings
Refer the device tree bindings doc.Documentation/devicetree/bindings/memory-controllers/synopsys.txt
For ZynqMP SOC device tree bindings doc
refer devicetree bindings doc
For Zynq SOC
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memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
}; |
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memory-controller@fd070000 {
compatible = "xlnx,zynqmp-ddrc-2.40a";
reg = <0x0 0xfd070000 0x0 0x30000>;
interrupt-parent = <&&gic>;
interrupts = <0 112 4>;
}; |
Mainline Status
In mainlineThis driver is in mainline.
Fixes related to coverity warning are not yet in mainline (~3 lines).
Test Procedure
Zynq
To test the EDAC driver on Zynq platform manually, below are the changes required in FSBL and U-Boot source:
FSBL changes:
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If the ECC is enabled on Zynq, then ram size will be reduced to half. So after ECC is enabled, the DDR region is 512MB.
In the "ps7_ddr_ecc_init" function in ps7_init.c file, reduce the length of the DDR region initialized to 500MB (Hex: 0x1F400000) instead of 512MB.
int ps7_ddr_ecc_init(void)
{
unsigned long LengthBytes = 0x1F400000; //PS7_DDR_LENGTH;
unsigned long SourceAddr = 0;
unsigned long DestAddr = PS7_XPAR_PS7_DDR_0_S_AXI_BASEADDR;
unsigned long Length = 0;
...
...
}
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