This page gives an overview of the bare-metal driver support for the Xilinx® LogiCORE™ IP Zynq Ultrascale+ MPSoC USB soft IP. 

Table of Contents

Introduction

This page gives an overview of the Zynq Ultrascale+ MPSoC usbpsu driver which is available as part of the Xilinx Vivado and SDK distribution.
This document explains USB 2.0 & 3.0 peripheral mode standalone configurations for MASS STORAGE and DFU gadgets

For more information,

Please refer to Chapter 31: USB3.0 Controller in ZynqMp TRM which includes links to the official documentation and resource utilization.

Please refer to Chapter 72: USB2.0 Controller in Versal TRM which includes links to the official documentation and resource utilization.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation and being available in the Xilinx Github repository. 

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usbpsu

The driver source code is organized into different folders.  The table below shows the usbpsu driver source organization. 

Driver Implementation

For a full list of features supported by this IP,

ZynqMp: Please refer to Chapter 31: USB3.0 Controller in ZynqMp TRM

Versal: Please refer to Chapter 72: USB2.0 Controller in Versal TRM

Features

Features Controller Support

The ZynqMP USB 3.0 Controller shall provide one 5.0Gbit/s USB channel using the PS internal GT as PHY.

• Two USB 2.0/3.0 controllers

• Compliant with USB 3.0 specs

• Compliant with xHCI standard

• Supports 5.0 Gbps data rate

• Support host and device modes

• Support On The Go (OTG) host/device selection

• Provide simultaneous operation of the USB2.0 and USB3.0 interfaces where applicable

  • In host mode, as required by the standard for speed negotiation and switching

  • In device mode, statically configured as USB2.0 or USB3.0

• 64-bit AXI master port with built-in DMA

• Register programming via AXI and/or APB slave ports

• Power management features: hibernation mode

• Support 44-bit address space

• Supports Link Power Management (LPM) transfers to save power when the bus is idle

Features Driver support

• Supports device mode only

• Supports LPM transfers

Known Issues and Limitations

• Host mode is not supported by the standalone driver

• Doesn't support hibernation

• Can't operate simultaneous USB 3.0/ 2.0 modes, need to restart example before changing modes

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package settings tab. 

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usbpsu/examples

Example Application Usage

Mass-Storage: USB Polled/Interrupt mode example

Mass storage profile can be tested by compiling xusbpsu_ch9_storage.c , xusbpsu_ch9_storage.h , xusbpsu_ch9.c , xusbpsu_ch9.h , xusbpsu_class_storage.c , xusbpsu_class_storage.h , xusbpsu_intr_example.c/xusbpsu_poll_example.c 
files together

USB 2.0 Peripheral Mode

The below gives the testing procedure of zynqmp USB standalone example which operates as a mass storage gadget

Testing procedure

• Download and run the generated USB 2.0 example ELF on board

• Debug prints you can see on com port(Teraterm/putty)
  the below prints should be seen on com port
  
  

  Open

  

• Connect board to standard host(Windows/Linux)machine USB 2.0 port.

Expected Output

• You will get a pop-up window on the Window machine for formatting the size 256MB
  After the format complete you can copy a file to the USB device
  
  

  Open

  

USB 3.0 Peripheral Mode

The below gives the testing procedure of zynqmp USB standalone example which operates as a mass storage gadget

Testing procedure

• Download and run the generated USB 3.0 example ELF on board

• Debug prints you can see on com port(Teraterm/putty)
  the below points should be seen on com port
  
  

   

• Connect board to standard host(Windows/Linux)machine USB 3.0 port.

Expected Output

• You will get a pop-up window on the Window machine for formatting the size 256MB
  After the format complete you can copy a file to the USB device

USB Composite Testing

Testing procedure

• Download and run the generated USB 3.0 example ELF on board

• Debug prints you can see on com port(Teraterm/putty)

Expected Output

Device Log:

• Connect the board to a standard host(Windows/Linux) machine USB port.

Host Log (Linux):

USB DFU Testing

The below gives the testing procedure of zynqmp USB DFU example

Testing procedure

On ZCU102 board side

• Download and run the generated dfu example

On HOST side
On Linux

• Install dfu-util binaries in linux host. Please refer http://dfu-util.sourceforge.net/build.html

• Connect DFU device (Alto device running DFU example)

• dfu-util –l (check our DFU Boot Image downloader)

• dfu-util –D boot.bin

On Windows
Install Windows driver for DFU devices in host machine

• Download Zadig tool from http://zadig.akeo.ie/ and install

• Connect DFU device (Alto device running DFU example)

• Open zadig and select DFU device and install WinUSB driver

Running dfu-util and downloading files

• Install DFU utils

• Launch 'cmd' (make sure your path is that where dfu-util.exe is)

• dfu-util –l (check our DFU Boot Image downloader)

• dfu-util –D boot.bin –t 1024

Expected Output

Example Design Architecture

Default Petalinux Design

Performance

The below performance results are observed using CrystalDiskMark tool on windows

USB 2.0:

USB 3.0:

Change Log

2023.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L321

2023.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.1/doc/ChangeLog#L153

2022.2

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.2/doc/ChangeLog#L151

2022.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.1/doc/ChangeLog#L126

2021.2

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.2/doc/ChangeLog#L221

2021.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L494

2020.2

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L350

2020.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L238

2019.2

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.2/doc/ChangeLog#L90

2019.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.1/doc/ChangeLog#L267

2018.3

https://github.com/Xilinx/embeddedsw/blob/release-2018.3/doc/ChangeLog#L307

2018.2

https://github.com/Xilinx/embeddedsw/blob/release-2018.2/doc/ChangeLog#L441

2018.1

https://github.com/Xilinx/embeddedsw/blob/release-2018.1/doc/ChangeLog#L332

2017.3

https://github.com/Xilinx/embeddedsw/blob/release-2017.3/doc/ChangeLog#L881

2017.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2017.1/doc/ChangeLog#L406

2016.4

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2016.4/doc/ChangeLog#L1049

2015.4

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2015.4/doc/ChangeLog#L258

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries