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HDMI FrameBuffer Example Design 2019.2

HDMI FrameBuffer Example Design 2019.2

Feb 12, 2020

 

 

1 Overview


The Zynq UltraScale+ MPSOC HDMI (High-bandwidth Digital Multimedia Interface) Example design is an embedded video application running on APU and PL, to showcase the connectivity solution under Linux with the optional HDCP (High-bandwidth Digital Content Protection) feature.

The design demonstrates the capture and display capability of HDMI interface implemented in PL enabling user to get the video data in and out of the FPGA with relative ease and the use of HDCP Revision 1.4/2.2 to securely send audio-visual data from/to an HDCP protected source/sink. Typically HDCP 2.2 is used to encrypt content at Ultra High Definition (UHD) while HDCP 1.4 is used as a legacy encryption scheme for lower resolutions.


2 Software Tools and System Requirements

 

2.1 Hardware


Required:

  • ZCU102 Evaluation Board with Production Silicon (Rev 1.0)

  • Monitor with HDMI input with up to UHD resolution (3840x2160@60Hz)

  • HDMI Premium Certified cables

  • Micro-USB cable, connected to laptop or desktop for the terminal emulator

  • SD card

 

2.2 Software


Required:



2.3 Licensing

  • Important: Certain material in this reference design is separately licensed by third parties and may be subject to the GNU General Public License version 2, the GNU Lesser General License version 2.1, or other licenses. The Third Party Library Sources zip file provides a copy of separately licensed material that is not included in the reference design.

  • You will need only the Vivado Design Suite license to build the design. You can evaluate for 30-days or purchase it here.

  • You will also require the HDMI IP Core evaluation license to build this design. You can request the IP evaluation license here.

  • The design comes in two flavors – one with HDCP feature and one without. For using HDCP feature, users need to have their own HDCP keys. Additionally users will need to implement HDCP IP. Xilinx provides the IP to implement HDCP encryption block but legally can only offer the IP to users who are HDCP2.2 adopters – list of HDCP adopters is verified here https://www.digital-cp.com/licensee-list. If you or your company is not a HDCP adopter, we recommend using the non-HDCP version of the design.


Steps to generate the license:

  1. Log in here with your work E-mail address (If you do not yet have an account, follow the steps under Create Account)

  2. Generate a license from “Create New Licenses” by checking "Vivado Design Suite, 30 Day Evaluation License"

 

  1. Under system information, give the host details.

  2. Proceed until you get the license agreement and accept it.

  3. The License (.lic file) will be sent to the email-id mentioned in the login details.

  4. Copy the license file locally and give the same path in the SDSoC license manager.

 

3 Design

 

3.1 Hardware


2 reference designs are available with different IP configuration to demonstrate the targeted features

  • 2 Pixels/Clock, 8-bit Color Depth with NO HDCP

  • 2 Pixels/Clock, 10-bit Color Depth with HDCP 1.4 & 2.2 (Demonstrates deep color and HDCP functionality)


The example design is built around the HDMI 1.4/2.0 Transmitter Subsystem (HDMI_TX_SS), HDMI 1.4/2.0 Receiver Subsystem (HDMI_RX_SS), Video PHY (VPHY) Controller core and leverages existing Xilinx IP cores to form the complete system. The VPHY Controller core has been configured for the HDMI application that allows transmission and reception of HDMI video/audio to and from the on-board HDMI 2.0 circuitry.


In pass-through mode, the VPHY Controller core recovers the high-speed serial video stream, converts it to parallel data stream, forwards it to the HDMI_RX_SS core, which extracts the video from the HDMI stream and converts it into AXI stream. The AXI video is connected to the Frame Buffer Write IP that writes this data into the DDR in the user specified memory format. On the display side, Frame Buffer Read IP reads the data from DDR and sends it to the HDMI_TX_SS core, which converts the AXI video back to an HDMI stream before being transmitted by the VPHY Controller core as a high-speed serial data stream.

3.2 Software Application


HDMI Pass-through application aka video_cmd is a user space application provided to demonstrate the end-to-end capture to display pipeline. No video processing is performed on the frames stored in memory. During initialization, video_cmd can detect a video source that is plugged into the RX port and then comes up in pass-through mode. If video_cmd does not find any source, it comes up in TPG mode and starts streaming SMPTE colorbars (generated by the open source modetest utility integrated into the software application) . video_cmd can also detect any change in the input like video source hot-plug, video source disconnect, resolution change, color format change, user input etc. and adapts accordingly.

If the user is running this app on a design that supports HDCP, the application expects the production HDCP keys to be available on the EEPROM (refer HDMI IP product guide pg235/236 for details) and prompts the user to enter the password during initialization. If the user enters correct password, the application retrieves HDCP keys from the EEPROM and loads them into the IP and enables the HDCP feature. 3 attempts are provided to enter correct password, failing which causes the application to start with HDCP feature disabled.

video_cmd is an interactive tool where the user can choose the action from following menu: