This page provides detailed information related to Design Module 13 - Xilinx Low Latency HLG SDI Audio Video Capture and Display with PL DDR.

Table of Contents

1 Overview

The primary goal of this Design is to demonstrate the capabilities of VCU hard block present in Zynq UltraScale+ EV devices. The TRD will serve as a platform to tune the performance parameters of VCU and arrive at optimal configurations for encoder and decoder blocks. It has also added an initial support of 8-channels audio.

This module enables the capture of the Hybrid Log Gamma(HLG) video from an SDI-Rx subsystem implemented in the PL. The Hybrid Log Gamma(HLG) video can be displayed through the SDI-Tx subsystem implemented in the PL. The module can stream-out and stream-in live captured video frames through an Ethernet interface. This module supports single-stream for XV20 pixel format. In this design, PL_DDR is used for decoding and PS_DDR for encoding so that DDR bandwidth would be enough to support high bandwidth VCU applications requiring simultaneous encoder and decoder operations and transcoding at 4k@60 FPS.

The VCU encoder and decoder operate in slice mode. An input frame is divided into multiple slices (8 or 16) horizontally. The encoder generates a slice_done interrupt at every end of the slice. Generated NAL unit data can be passed to a downstream element immediately without waiting for the frame_done interrupt. The VCU decoder also starts processing data as soon as one slice of data is ready in its circular buffer instead of waiting for complete frame data. The Sync IP does an AXI transaction-level tracking so that the producer and consumer can be synchronized at the granularity of AXI transactions instead of granularity at the video buffer level. Sync IP is responsible for synchronizing buffers between Capture DMA and VCU encoder as both works on the same buffer.

The capture element (FB write DMA) writes video buffers in raster-scan order. SyncIP monitors the buffer level while the capture element is writing into DRAM and allows the encoder to read input buffer data if the requested data is already written by DMA, otherwise it blocks the encoder until DMA completes its writes. On the decoder side, the VCU decoder writes decoded video buffer data into DRAM in block-raster scan order and displays reads data in raster-scan order. To avoid display under-run problems, the software ensures a phase difference of "~frame_period/2", so that decoder is ahead compared to display.

This module supports the Encoding-Decoding and Transmission of Hybrid Log Gamma (HLG) video along with backward compatible Standard Dynamic Range (SDR) for SDI. It provides the ability to encode a wide dynamic range, while still being compatible with the existing transmission standards in the standard dynamic range (SDR) region. This HLG format encodes the HDR and SDR information in single signal enabling HDR-compatible TVs to display an enhanced image. Unlike HDR it does not have any metadata, rather it will use the Alternative transfer characteristics (ATC) and Supplemental Enhanced Information (SEI) in the Video Usability Information (VUI) to add extra encoding details.

From VCU point of view, there are two "types" of HLG, which you can enable:

1. There is a HLG-SDR Backwards Compatible Mode, which uses the BT2020 value in the SPS VUI parameters instead of the HLG transfer characteristics. Then the VCU encoder will insert an 'Alternative Transfer Characteristics' (ATC) SEI with the HLG value. See the below video frame snapshot captured in the stream-eye: