Table of Contents
- You have a ZCU102 development board.
- You have a linux machine to build images.
- You have used the Petalinux (2018.1 or later) to build.
- You have familiar with Vivado (2018.1 or later release)
Power off suspend is the new feature in the Xilinx Power Management where APU, RPU and PMU will be power down and current state will be stored on DDR Memory.
Except clock all other peripherals such as UART,OCM,TCM will be powered down. MSP430 processor will be used as source for waking up the system.
Power Off Suspend has been implemented for the ZCU102
board only (testing was done on a single board at room temperature, so PVT testing was not performed).
Steps for Enabling Power off Suspend feature
Create HDF with GPO2 polarity to High
Source petalinux settings.
Create petalinux project using below command.
- Start Xilinx Vivado 2018.1
- Open existing petalinux project from Vivado. (Located at <plnx-proj-root-dir>/hardware/xilinx-zcu102-2018.1/xilinx-zcu102-2018.1.xpr)
- Open block design, customize block design using double click on "Zynq UltraScale+ MPSoC" block. (or right click and then click on "Customize Block" option)
- On the "Page Navigator" bar, click on I/O configuration.
- Go to Low Speed -> IO Peripherals -> PMU -> GPO2. Default polarity of GPO2 is low. Change GPO2 polarity to high as per below snapshot and click "OK".
- In the Flow Navigator → PROGRAM and DEBUG, click on "Generate Bitstream" option.
- Export HDF file
- Go to File → Export → Export Hardware
- Check "Include bitstream in HDF" option. Set export path if required or keep it default(<Local to Project>). Click "OK"
- In case of default path, HDF file will be generated at <workspace>/<project_name>/<project_name>.sdk/<block_name>.hdf.
Build images using Petalinux
Source petalinux settings:
Create petalinux project using below command:
Configure petalinux using custom HDF (generated in previuos steps) using below command:
- Enable ZynqMP firmware debugfs config in Linux kernel (ZYNQMP_FIRMWARE_DEBUG) using below steps:
- Run "petalinux-config -c kernel" command.
- Go to Firmware Drivers -> Zynq MPSoC Firmware Drivers and enable Xilinx Zynq MPSoC firmware debug APIs.
- Save configuration and exit from that.
- Enable POS related build flag in FSBL (ENABLE_POS) using below steps:
- Enable POS related build flag in PMUFW (ENABLE_POS) using below steps:
Build petalinux using below command:
Run below command inside petalinux root directory to generate BOOT.BIN:
- Built images (BOOT.BIN and image.ub) are present at <plnx_root_dir>/images/linux/
Please click on the link to read about MSP430 procedure -http://www.wiki.xilinx.com/Zynq+UltraScale%EF%BC%8B+MPSoC+Power+Advantage+Tool+part+7+-+Building+and+Running+the+MSP430+Design+from+Source
For enabling power off suspend feature user needs to replace the current MSP430.txt file with the new MSP430.txt file.
Update MSP430 firmware with the image below:
Steps to do Power off Suspend
To suspend, type this in the Linux console:
(For 2018.1 and 2018.2)
After using above command on the linux console, system will go to power off suspend mode.
In power off suspend
LED such as DS24, DS26,DS21, PSPLL and PSAUX should be in off state.
If user uses power advantage tool then user will see that power reading of FPD, LPD and PL domain should be 0 mW.
Note:- At a time user can either use power adavantage tool or MSP430 console as both uses same com port.
For resuming the linux user needs to open UART Interface 3 port.
Go to Device Manager -> Ports
See the com port number for UART Interface 3
Now go to Tera Term/PuTTY (for opening port) and open this port. Here Ex. COM9 at baud rate - 1152000.
Now to resume, type this in the MSP430 console i.e. on port COM9:
After sending @wake signal to com port system will wake up and user can see logs on the Linux console.
Note: Since PL is powered down during PoS, user application needs to take care of loading the PL bitstream explicitly
after resuming from PoS if any application is using the PL resources.