Zynq UltraScale+ PL Masters

This page describes details needed to make an AXI Master in the PL function with Linux and bare metal. The Programmable Logic (PL) of the FPGA provides the flexibility to move data using AXI Masters such as DMA or custom IP. 

Table of Contents

1 General Tips

1.1 64 Bit Addressing on Zynq UltraScale+ MPSOC

The ARM A53 CPUs of MPSOC are 64 bits by default. The ZCU102 board has 4 GB of DDR but only 2 GB is in the lower 32 bit address range and the other 2 GB is in the 64 bit address range. Linux uses all the memory such that 64 addresses are required for PL Masters. At the time of the 2017.4 release, 64 bit addressing is not the default in the system with PL Masters. IP cores such as AXI DMA default to 32 bit addressing. An Answer Record, AR70413, provides an example AXI DMA system with details.

1.1.1 Vivado Settings For High Address

The following illustration shows how to turn on High Address for MPSOC in Vivado. The feature allows slaves in the upper 64 bits, such as high DDR, to be accessed from PL Masters.

1.1.2 Vivado Settings For 64 Bit Addressing With AXI DMA

Each IP Core which is an AXI Master may require settings to enable 64 bit addressing. The following illustration is an example of the AXI DMA IP and turning on 64 bit addressing.

1.1.3 Vivado Address Editor And High DDR With AXI DMA

The following illustration shows the DDR high memory is visible to the AXI DMA.

1.1.4 Workarounds

A system which is failing with a PL master in Linux can be made to work to verify the issue by restricting the amount of memory that Linux has with the kernel command line.
The following command illustrates in u-boot how to alter the amount of memory allowing only the lower 2 GB of 32 bit addressable memory.

u-boot->setenv bootargs "<existing kernel command line> mem=2G"
u-boot->run bootcmd

Related Links

© Copyright 2019 - 2022 Xilinx Inc. Privacy Policy