2018.2 Linux and DTG Release Notes

Linux Changes

Module Name	Driver Location	Feature Changes	Link
FPGA Manager/ZynqMP PL programming	drivers/fpga/zynqmp-fpga.c	Added Support for Partial Reconfiguration	http://www.wiki.xilinx.com/Solution+ZynqMP+PL+Programming

Linux Bug Fixes

drivers/usb/gadget/udc/udc-xilinx.c

Module Name	Driver Location	Bug Fixes	Link
Zynq and ZynqMP SD Controller	drivers/mmc/host/sdhci-of-arasan.c	Removed quirk for broken base clock in SDHCI driver	http://www.wiki.xilinx.com/SD%20controller
GMII2RGMII	drivers/net/phy/xilinx_gmii2rgmii.c	Add check for external phy driver	http://www.wiki.xilinx.com/Xilinx+GMII2RGMII+convertor
RFdc	XilinxProcessorIPLib/drivers/rfdc/src/ (user space driver available in embeddedsw)	Adjust calculated latency by sysref period, where doing so results in closer alignment to the target latency. Removed CalibrationMode check for DAC in XRFdc_GetMixerSettings() and XRFdc_GetNyquistZone() APIs	http://www.wiki.xilinx.com/RFdc%20Linux%20driver
Zynq PL35X Nand	drivers/mtd/nand/pl35x_nand.c	Fix for incorrect ooblayout offset update	http://www.wiki.xilinx.com/Zynq%20Pl353%20SMC%20and%20NAND%20drivers
ZynqMP USB	drivers/usb/dwc3/gadget.c	Fix ISOC transfers for USB Video Class	http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+USB+device+driver
AXI USB	drivers/usb/gadget/udc/udc-xilinx.c	Add clock framework support to axi usb driver	http://www.wiki.xilinx.com/AXI+USB+gadget+driver

DTG Feature Changes

Module Name	Feature Changes	Link
USB	Add support for USB 2.0	https://github.com/Xilinx/device-tree-xlnx/commit/84b8035b562256a85e2c130d44f60e2b4b97834d
sdfec	Update the sdfec parameters	https://github.com/Xilinx/device-tree-xlnx/commit/cdc5afcea1af9c2299258e10634b074d61f284ed
axi_pcie	Update the interrupt names for pcie	https://github.com/Xilinx/device-tree-xlnx/commit/0fed687b45dc813ecfa3e4167b0b533346851da0

DTG Bug Fixes

Module Name	Bug Fixes	Link
axi_dma	axi_dma hang issue	https://github.com/Xilinx/device-tree-xlnx/commit/afc83a1a4779b80b0360ef366ca7d67b9a7169de
axi_pcie	Update the range property in axi_pcie	https://github.com/Xilinx/device-tree-xlnx/commit/3d88b4caf5809e000b5c5665299f0783ae09c072
axi_Ethernet	Update the xlnx,num-queues in axi_Ethernet	https://github.com/Xilinx/device-tree-xlnx/commit/36b54d4d2a7a41b81880cf73e83f98c84481fe1b
common	Update the reg property for external axi interface	https://github.com/Xilinx/device-tree-xlnx/commit/a2d3a1bfae446360200a4f75f7ac44d783a68ffe
axi_dma	Fix the clock node for axi dma	https://github.com/Xilinx/device-tree-xlnx/commit/0a3927265e93d601b5a147b3423d26005a851da4
axi_vcu	Fix the vcu clock node	https://github.com/Xilinx/device-tree-xlnx/commit/a680ccf8d75217d519a284b11f8b7d37c025b8ba

Answer Records (ARs)

Module Name	AR Title	AR Link
Ethernet GEM	Zynq UltraScale+ MPSoC: PetaLinux Warm-Restart BSP fails to wake up Ethernet	https://www.xilinx.com/support/answers/71028.html
RFdc	RFSoC - (PG269) States incorrect DAC supported sampling rate, and Minimum value of Reference clock	https://www.xilinx.com/support/answers/71229.html

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