Table of Contents

The purpose of this page is to describe the Linux DRM driver for Xilinx SDI-Tx Soft IP for Zynq Ultrascale+ MPSOC

Introduction

The Society of Motion Picture and Television Engineers (SMPTE) UHD-SDI transmitter subsystem implements a SDI transmit interface in accordance to the serial digital interface (SDI) family of standards. The subsystem accepts video from AXI-4 Stream Video interface and outputs. Native Video stream, and allows for fast selection of the top-level parameters and automates most of the lower level parameterization. The AXI4-stream video interface allows a seamless interface to other AXI4-Stream-based subsystems. The SMPTE UHD-SDI Transmitter Subsystem allows you to quickly create systems based on SMPTE SDI protocols. It accepts AXI-4 Video stream and outputs native SDI stream by using Xilinx transceivers as physical layer. The top level customization parameters select the required hardware blocks needed to build the subsystem.

Driver Overview

SDITx is the last node in the display pipeline. The Linux driver is implemented as a sub-component of the Xilinx DRM KMS bridge driver and implements the encoder/connector interface. The subsystem includes the video timing controller(VTC), Axi-4 Stream to Video, SDI Tx bridge and Tx sub-core. Driver implements the DRM callbacks to read the supported resolutions from driver and provide to DRM framework anytime queried. On mode change request from user application driver works in conjunction with DRM framework to validate the requested mode to ensure the stream can be generated by Tx core and is supported by the driver. If requested mode is supported the driver will configure Tx sub-core for new mode and the configure the video timing controller (VTC) to generate requisite video timing for it. This driver also supports user parameters for SDi-mode, number of data stream and fractional frame rates.

IP/Driver Features

Missing Features / Known Issues / Limitations in Driver

• *Multiple instances capability not tested

• **Few fractional fps with interlaced modes are recognized as round off value on SDI tester equipment

  • ex: 1920x1080i@47.95 shown 48 fps on Omnitek.

• Tested with Phabrix and Omnitek Ultra4K

Kernel Configuration Options for Driver

>=2018.1

CONFIG_DRM_XLNX_SDI should be enabled. This depends on CONFIG_DRM_XLNX and CONFIG_DRM

<2018.1

CONFIG_DRM_XILINX_SDI and CONFIG_VIDEO_XILINX should be enabled

Device Tree Binding

The dts node should be defined with correct hardware configuration. How to define the node is documented in

>=2025.1 onwards: linux-xlnx/Documentation/devicetree/bindings/display/xlnx/xlnx,sdi-tx.yaml at master · Xilinx/linux-xlnx · GitHub

>=2018.1

https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/display/xlnx/xlnx%2Csdi-tx.txt

<2018.1

Documentation/devicetree/bindings/drm/xilinx/sdi.txt

Below is the example device tree for a design where the display pipeline flows from DDR memory through a framebuffer read DMA to an SDI transmitter. Below device tree nodes are generated by SDT.

&amba_pl {
misc_clk_100: misc_clk_100 {
#clock-cells = <0>;
clock-frequency = <100000000>;
compatible = "fixed-clock";
};
misc_clk_297: misc_clk_297 {
#clock-cells = <0>;
clock-frequency = <297000000>;
compatible = "fixed-clock";
};
misc_clk_300: misc_clk_300 {
#clock-cells = <0>;
clock-frequency = <300000000>;
compatible = "fixed-clock";
};
};
&si5328 {
compatible = "silabs,si5328";
reg =<0x69>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
/*input clock(s); the xtal is hard-wired on the zcu106 board /
clock-names = "xtal";
/ output clocks */
clk0 {
reg = <0>;
/*QPLL1 reference clock output frequency */
clock-frequency = <148500000>;
};
};
&si570_2 {
clock-frequency = <148500000>;
};
&v_smpte_uhdsdi_tx_ss {
clock-names = "s_axi_aclk" , "sdi_tx_clk" , "video_in_clk";
clocks = <&misc_clk_100>, <&si5328 0>, <&misc_clk_297>;
phy-reset-gpio = <&axi_gpio_0 0 0 0>;
xlnx,qpll1_enabled = <0x1>;
};
&v_smpte_uhdsdi_rx_ss {
clock-names = "s_axi_aclk" , "sdi_rx_clk" , "video_out_clk";
clocks = <&misc_clk_100>, <&si570_2>, <&misc_clk_297>;
reset_gt-gpios = <&axi_gpio_1 0 0 0>;
};

Test Procedure

SDI-Tx can be manually configured to generate the required mode. An open source utility like modetest can be used to configure the display pipeline. Pipeline: DDR ==> Framebuffer read ==> SDI-Tx
Sample command to set a mode is shown below

• modetest –M xlnx -s <connector_id>[@<crtc_id>]:<mode>[-<vrefresh>][@<format> - w <connector_id>:<property_name>:<property_value>

For ex:

• modetest -M xlnx -s 27:1280x720-30@YUYV -w 27:sdi_mode:0 -w 27:sdi_data_stream:2 -w 27:is_frac:0

Above command will generate a color bar pattern at requested resolution in DDR, configures the DMA to read the frame from DDR and configures the SDI-TX for said resolution. As a final result Color Bar at defined resolution should be visible on screen.

Note:

<2018.1:

Test command will be as follows:

modetest –M xilinx_drm -s <connector_id>[@<crtc_id>]:<mode>[-<vrefresh>][@<format> - w <connector_id>:<property_name>:<property_value>

Debug capability

The driver debug messages can be enabled by adding "#define DEBUG" at the top of the file. All debug prints are sent to serial console and can be viewed in kernel dmesg buffer.

Boards Supported

Driver has been tested on ZCU106 Rev1.0

Known Issues

• AR68767 - SMPTE UHD-SDI Transmitter Subsystem - Release Notes and Known Issues for the Vivado 2017.3 tool and later versions.

Changelog

2025.2

• Summary:

  • No changes

2025.1

• Summary:

  • drm: xlnx: sdi: Use dev_err_probe() helper

  • drm: xlnx: sdi: Simpify using devm_clk_get_enabled()

  • drm: xlnx: sdi: Use devm_platform_ioremap_resource()

     

2024.2

• Summary:

  • No changes on drivers

  • Hence, for device tree related changes please refer: Video PL-IP Linux Drivers SDT Reference - Xilinx Wiki - Confluence

2024.1

• Summary:

  • No changes 

2023.1 & 2023.2

• Summary:

  • No changes 

2022.2

• Summary:

  • Add an extra check to get the correct timing table index.

  • reset the gt-phy based on device tree property.

  • Fix the typo in kernel-doc.

  • Add YUV444 format support. 

  • HFR feature support

  • Fix coding style (double space)

• Commits:

  • drm: xlnx: sdi: Add extra check to get the correct timing table index 

  • drm: xlnx: sdi: reset gt-phy based on device tree property 

  • drm: xlnx: sdi: Fix typo in kernel-doc 

  • drm: xlnx: sdi: YUV444 format support 

  • drm: xlnx: sdi: HFR feature support

  • drm: xlnx: sdi: Fix coding style (double space)

2022.1

• Summary:

  • No changes 

2021.2

• Summary:

  • No changes 

 2021.1

• Summary:

  • Updated sdi audio parameters

• Commits:

  • d4ce79 drm: xlnx: sdi: Update sdi audio parameters

2020.2

• Summary:

  • Add mode_valid helper function

  • Add supported EOTF's list to connector

  • Add support to non-picxo designs

  • Update EOTF and colorimetry fields in payload

  • Fix dynamic clock config to support QPLL1 reset

  • Added clock config to support integer and fractional framerate

• Commits:

  • 26518e drm: xlnx: sdi: Add mode_valid helper function

  • 13e7b5 drm: xlnx: sdi: Add supported EOTF's list to connector

  • 801956 drm: xlnx: sdi: Add support to non-picxo designs

  • d8b6fd drm: xlnx: sdi: Update EOTF and colorimetry fields in payload

  • 6102a0 drm: xlnx: sdi: Fix dynamic clock config to support QPLL1 reset

  • 06add1 drm: xlnx: sdi: Add clock config to support integer and fractional framerate

2020.1

• Summary:

  • Updated irq name

• Commits:

  • 54aef6 drm: xlnx: sdi: Use the named IRQ when available

2019.2

• No update

2019.1

• Summary:

  • Updated drm property creation logic

  • Added clock framework support

• Commits:

  • aa0ca2 drm: xlnx: sdi: Updated drm property creation logic

  • d4a2ef drm: xlnx: sdi: Add clock framework support

2018.3

• Summary:

  • Added bridge disable under sdi disable

  • Fix clearing en_st352 and use_ds2_3ga drm properties

  • Added support to DS2 payload in 3GA mode

  • Add ST352 payload insertion in chroma stream

  • Enabled support to ancillary data

  • Added video mode hdisplay and flags to shared data

  • Enabled audio

  • Fixed Vertical field 1 size calculation

  • Fixed HSIZE calculation

• Commits:

  • 9b071b drm: xlnx: sdi: Disable bridge instance

  • 883a92 drm: xlnx: sdi: Fix clearing en_st352_c and use_ds2_3ga drm properties

  • 484c16 drm: xlnx: sdi:  Add support for DS2 payload in 3GA mode

  • 3358cc drm: xlnx: sdi: Add ST352 payload insertion in Chroma stream

  • b755ed drm: xlnx: sdi: Enable support for ancillary data

  • fef944 drm: xlnx: sdi: Add video mode hdisplay, flags to the shared data

  • d42f4f drm: xlnx: sdi: Enable audio

  • c7cacf drm: xlnx: sdi: Fix the Vertical Field 1 Size calculation

  • 5d4a1b drm: xlnx: sdi: Fix the HSIZE calculation

2018.2

• Summary

  • No change

2018.1

• Summary:

  • Added YUV420 support

  • Added xlnx bridge support

  • Added initial version based on xlnx drm framework

• Commits:

  • 0cd279 drm: xlnx: sdi: Adding yuv 420 support

  • 4855d7 drm: xlnx: sdi: Adding xlnx bridge support

  • 5d4a1b drm: xlnx: sdi:

2017.4

• Added vblank support

• Added psf mode support

• Added 3G-B and 12G support

• Driver in drivers/gpu/drm/Xilinx/Xilinx_drm_sdi.c and maintained at a special branch
  https://github.com/Xilinx/linux-xlnx/tree/2017.3_video_ea

2017.3

• Initial version.

• Driver in drivers/gpu/drm/Xilinx/Xilinx_drm_sdi.c and maintained at a special branch
  https://github.com/Xilinx/linux-xlnx/tree/2017.3_video_ea

Related Links

• SDI-TX Product Guide

• Xilinx Linux drivers

• Xilinx DRM drivers