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Zynq Base TRD 2014.4

Zynq Base TRD 2014.4

Sept 24, 2018

 

Zynq Base TRD 2014.4

 

Table of Contents

1 Introduction

1.1 About the Base TRD

1.2 Download the TRD

1.3 Base TRD Package Contents

1.4 Prerequisites

1.5 Known Issues

2 Run the TRD demo

2.1 Hardware Setup Requirements

2.2 Board Setup

2.3 Run Qt GUI Application in 1080p mode

2.4 Run Qt GUI Application in 720p mode

2.5 Run UART Menu Application in 1080p mode

3 Vivado

3.1 Building the Bitstream

3.2 Steps for exporting the hardware platform to XSDK

4 Vivado HLS

5 Petalinux

5.1 Installation of Petalinux SDK

5.2 Build Petalinux images

5.2.1 Building petalinux images (No FMC)

5.2.2 Building petalinux images (FMC)

5.3 Generate BOOT image for Zynq

6 XSDK

6.1 Import project

6.2 Build project

6.3 Deploy and Debugging applications

7 References

8 Appendix

8.1 EDID Extended display identification data

History

Vivado 2014.2 Targeted Base Reference Design
Vivado 2013.4 Targeted Base Reference Design
Vivado 2013.3 Targeted Base Reference Design
Vivado 2013.2 Targeted Base Reference Design
ISE DS 14.5 Targeted Base Reference Design
ISE DS 14.4 Targeted Base Reference Design
ISE DS 14.3 Targeted Base Reference Design
ISE DS 14.2 Targeted Base Reference Design
ISE DS 14.1 Targeted Base Reference Design

1 Introduction


This page provides instructions on how to build various components of the Zynq Base Targeted Reference Design (TRD) and how to setup the hardware platform and run the design on the ZC702 Evaluation Kit. The ZC702 Evaluation kit is based on a XC7Z020 CLG484-1 Zynq-7000 SoC device.

1.1 About the Base TRD

The Base TRD is an embedded video processing application designed to showcase various features and capabilities of the Zynq Z-7020 SoC device for the embedded domain. The Base TRD consists of two elements: The Zynq-7000 SoC Processing System (PS) and a video processing pipeline implemented in Programmable Logic (PL). The SoC allows the user to implement a video processing algorithm that performs edge detection on an image (Sobel filter) either as a software program running on the Zynq-7000 SoC based PS or as a hardware accelerator inside the SoC based PL. The Base TRD demonstrates how the user can seamlessly switch between a software or a hardware implementation and evaluate the cost and benefit of each implementation. The TRD also demonstrates the value of offloading computation-intensive tasks onto PL, thereby freeing the CPU resources to be available for user-specific applications. For additional , please refer to UG925: Zynq-7000 SoC: ZC702 Base Targeted Reference Design User Guide.

1.2 Download the TRD

An archive with the TRD files can be downloaded here .

1.3 Base TRD Package Contents

The Zynq Base TRD package is released with the source code, Xilinx Vivado and SDK projects, and an SD card image that enables the user to run the video demonstration and software application. It also includes the binaries necessary to configure and boot the Zynq-7000 SoC board. This wiki page assumes the user has already downloaded the Base TRD package and extracted its contents to the Base TRD home directory referred to as ZYNQ_TRD_HOME in this wiki.


1.4 Prerequisites

Note: The provided logiCVC evaluation IP core has a 1 hour timeout built-in such that the display freezes after the timer expires. The pre-built bitfile and boot images are built from a full logiCVC IP core and don't expire.

1.5 Known Issues

  • Test Pattern Generator (TPG) version 5 is used instead of version 6 (latest) to avoid TPG going out of frame boundary when video source is changed. In TPG selection, when the bouncing box touches the boundary of the monitor a horizontal line appears on the monitor.

  • Occasionally on some hardware set-ups ADV7611 I2C slave returns NACK for I2C transaction. <adv7611 12-004c: not an adv7611 on address 0x98>.The workaround is to reboot the system.

  • HDMI input is not working. The PG signal does not assert by default on early ZC702 boards. To be FMC compliant, the PG signal must be asserted when power rails are good. See AR51438 for solution.

2 Run the TRD demo


This section provides step by step instructions on how to bring up the ZC702 board for video demonstration part of the TRD and running different video demonstrations
out of the box.
The ZC702 Evaluation Kit comes with an SD-MMC card pre-loaded with binaries that enable the user to run the video demonstration and software applications.
It also includes the binaries necessary to configure and boot the Zynq-7000 SoC based ZC702 board.

Note:
a) If the evaluation kit design files were downloaded online, copy the entire folder content from $ZYNQ_TRD_HOME/ready_to_test onto the primary partition of the SD-MMC card which is formatted as FAT32 using a SD-MMC card reader.
b) Petalinux console login details:-
User : root
Password : root
c) In case user has optional FPGA Mezzanine Card (FMC) setup
ready_to_test/devicetree_fmc.dtb is renamed to devicetree.dtb and copy it to primary partition of SD-MMC card along with

  • BOOT.BIN

  • autostart.sh

  • devicetree.dtb

  • uImage

  • uramdisk.image.gz

  • bin/ __

    • |- run_video.sh

    • |- video_cmd

    • |- video_qt


2.1 Hardware Setup Requirements


Requirements for TRD Linux application demo setup

  • The ZC702 evaluation board with the XC7Z020 CLG484-1 part

  • AC power adapter (12 VDC)

  • Optional: An USB Type-A to USB Mini-B cable (for UART communications) and a Tera Term Pro (or similar) UART terminal program.

  • USB-UART drivers from Silicon Labs

  • A HDMI cable.

  • Optional: FMC (FPGA Mezzanine Card).

  • Optional: External Video Source e.g. Roku HD Streaming player.

  • A SD-MMC flash card containing TRD binaries formatted with FAT32. The SD-MMC is pre-loaded with required binaries in its first partition. The pre-loaded binaries include :

    • BOOT.BIN

    • uImage

    • devicetree.dtb

    • devicetree_fmc.dtb

    • uramdisk.image.gz

    • autostart.sh

    • bin/ __

      • |- run_video.sh

      • |- video_cmd

      • |- video_qt

  • An USB Micro-B to female Adaptor with USB hub is needed for connecting a keyboard and a mouse.

  • An USB mouse and keyboard.

  • A display monitor that supports HD resolutions: 1920 x 1080p @ 60 Hz, and 1280 x 720 @ 60 Hz(if the user also want to validate TRD with 720p video output)


Note:
It is recommended to use ZC702 production board.
TRD binaries has been tested with a Asus VS228 display monitor. However, the examples should work well with any HDMI-compatible output device provided it supports 720/1080p resolution in its EDID database.

2.2 Board Setup


Steps for setting the board

Connect the cables as shown in figure below to prepare the ZC702 board to run the TRD video demo applications.



  • Optional: Connect the HDMI FMC card (BD-FMC-IMAGEON-G).

  • Connect a display monitor to the HDMI out port of the ZC702 board using a HDMI cable.

  • Connect a keyboard and mouse to an USB hub, which is connected to the ZC702 board Micro-B USB connector. (Keyboard is optional if just using the mouse in the Qt GUI)

  • Optional: Connect an USB Mini-B cable into the Mini USB port J17 labeled USB UART on the ZC702 board and the USB Type-A cable end into an open USB port on the host PC for UART communications.

  • Connect the power supply to the ZC702 board. Do not switch the power on.

  • Insert a SD-MMC memory card, which contains the TRD binaries, into the SD slot on the ZC702 board.

  • Make sure the switches are set as shown in figure below, which allows the ZC702 board to boot from the SD-MMC card.


Note: The older ZC702 rev.x version boards does not have switches and contains jumpers. Use the following jumper settings: J21: 2-3, J20: 2-3, J22: 1-2, J25: 1-2, J26: 2-3

2.3 Run Qt GUI Application in 1080p mode


A Linux application with Qt-based GUI is provided with the package included on the SD-MMC memory card. This application provides options to user to exercise different modes of the video demonstration. The Qt application can be used in minimize / maximize mode. User can select Test Pattern Generator (TPG) video or External video source (requires the HDMI FMC card and an external video source). The transparency slider is provided to control the GUI transparency.
User can select to process a sobel filter (run as software code on the Zynq PS ) or in hardware (run in the FPGA fabric as a hardware IP core).
User can configure sobel filter controls i.e. Set sobel filter in invert/non-invert mode and control sobel sensitivity using sensitivity slider on QT GUI.

Powering on the Qt-based GUI application demo

  • Make sure the monitor is set for HDMI or DVI 1920x1080 resolution. (Typically if a monitor has an HDMI input port, it will auto select for 1080P.@60Hz If it does not, then sometimes the video displayed will be odd)

  • Turn on power switch SW11.

Note: the Linux image and Qt based GUI application will be loaded from the SD-MMC memory card.

  • The Linux image will load and be frame buffer console is displayed on the HDMI 1080P monitor.

  • The Linux Qt based GUI will load



Running the Qt-based GUI application demo

  • When the GUI starts up, you will see that there is no video pattern or external video being processed. You will see that the the CPU graph trace is at a low level of video processing activity. The AXI bus HP port 0 is utilized around 1Gb/s which is just passing the GUI data, but not processing any video data out the HDMI port. The AXI bus Port 1 is also not active, as this is the port that will interface to the FPGA fabric, and at this time there is not activity on this AXI bus.

  • The user can click Help for short messages and information about the control window of the QT application.



  • Click the Enable Video check box. After enabling video , user will see that the GUI starts to display a locally generated test pattern with a moving box around the screen. User will not see much change in the CPU graph trace, and there is not a lot of processing over head to do this pass through of the video test pattern. Level of activity on the AXI bus HP port 0 jumps up, as more data is being passed out the HDMI AXI bus port.



  • Click the Sobel Mode to Software. Users see that the GUI starts to display the edge detecting effect of the sobel filter. Notice that the video is "jerky" and the moving box jumps around. CPUx has gone to about 100% bandwidth utilization. This is because the the sobel filter is being processed entirely in code run on CPUx. .




Exercise different options by pressing the buttons available in the GUI to evaluate the different use cases mentioned in following
Table.

Use Case

Video source

Use Case

Video source

1

Test Pattern Generator

2

External video


NOTE: External video is applicable only if:
a) Ready to test : ready_to_test/devicetree_fmc.dtb is renamed to devicetree.dtb and copied to SD partition.
b) In "Petalinux" section step 5.2.2 is selected.


Filter mode


Filter mode

6

None / SW / HW

Video source control modes are explained as follows:

  • TPG interference

  • External video (available with the optional ZVIK FMC module)


Sobel Filter modes are explained as follows:

  • Sobel OFF No processing done. Sobel filter is bypassed.

  • Sobel – SW Video processing (edge-detection filter) done by software code running on the PS.

  • Sobel – HW Video processing (edge-detection filtering) done by PL. Observe CPU utilization going down (to approximately 0) and the frame rate jumping to 60 fps.


While exercising the modes described above, one can observe AXI bus bandwidth utilization and CPU utilization on the graphs in the Qt GUI application.
Click Exit button on the GUI using the mouse to quit the application and return the user to linux console.

The application can be restarted by typing the following at the Linux command prompt:

zynq> run_video.sh -qt -r 1920x1080

2.4 Run Qt GUI Application in 720p mode


Prerequisite:
Monitor supporting 720p mode, as current design has a strict check for supported resolution.
For more information refer to Appendix 8.1 EDID section.

Command line resolution switch utility is added to dynamically change the resolution .
To use this feature application has to be started using -r option followed by input resolution.
Steps for Running QT based GUI in 720p mode.
a) Follow similar steps as mentioned in 2.3 subsection.
b) Exit QT application by clicking on Exit button.
c) Type these commands at the Linux command prompt into the host PC based terminal

zynq> run_video.sh -qt -r 1280x720

2.5 Run UART Menu Application in 1080p mode


A Linux application with command line menu is also provided with the package. This application provides options to the user to exercise different modes of the video demonstration over UART communications.

Note: The default Linux device tree binary file configures the video output resolution to 1080p @60Hz.
After setting the board as explained in Section 2.2, running the UART menu based application is explained in this section.

Steps for running the UART Menu-Based application demo

Power on the ZC702 board.
Start the installed UART terminal program on your host PC (e.g., Tera Term on a Windows PC, GtkTerm on a Linux PC).

Use the following UART configuration: Baud rate = 115200, bits = 8, parity = none, and stop bits = 1.
Note: This step is required to view debug information or to run the UART Menu-Based Demonstration application.

Wait for the ZC702 board to be configured and booted with Linux. After approximately 2 minutes, a XILINX ZYNQ banner displays on the monitor.
The Qt-based video demonstration application starts. The GUI application shows up at the bottom of the display monitor.
Click Exit button on the GUI using the mouse to quit the application and return the user to Linux console.

Go to the UART terminal started on the host PC.
Type these commands at the Linux command prompt into the host PC based UART terminal:

zynq> run_video.sh -cmd

The default resolution is 1920x1080.
The menu-based video application demonstration starts as shown in the Figure:




Exercise different options by entering the use case number displayed in the below Table against
Enter your choice : on the terminal.

Table.

Use Case

Video source

Use Case

Video source

1

Test Pattern Generator

2

External video


NOTE: External video is applicable only if:
a) Ready to test : ready_to_test/devicetree_fmc.dtb is renamed to devicetree.dtb and copied to SD partition.
b) In "Petalinux" section step 5.2.2 is selected.


Filter mode


Filter mode

6

None / SW / HW

Command line resolution switch utility is added to dynamically change the resolution .Enter 0 to exit the application and return to the command prompt.

2.6 Run UART Menu Application in 720p mode

Prerequisite: Monitor supporting 720p mode as current design has a strict check for supported resolution.
For more information refer to Appendix 8.1 EDID section.

To use this feature application has to be started using -r option followed by input resolution.

Steps for Running UART Menu based Demonstration Application in 720p mode.
a) Follow similar steps as mentioned in 2.5 subsection.
b) Exit UART application [enter 0 to exit ].
c)Type these commands at the Linux command prompt into the host PC based terminal:

zynq> run_video.sh -cmd -r 1280x720

3 Vivado

This section explains how to generate the FPGA hardware bitstream using the Xilinx Vivado tool and how to export the hardware platform to Xilinx Software Development Kit (XSDK) for software application development.

3.1 Building the Bitstream


Steps for building the FPGA hardware bitstream

Launch Vivado :

  • On Windows 7, select Start > All Programs > Xilinx Design Tools > Vivado 2014.4 > Vivado 2014.4

  • On Linux, enter vivado at the command prompt.


NOTE for Windows users: Copy directory 'vivado' that is at '$ZYNQ_TRD_HOME/hardware/' to a drive directly because of windows file path limit (255 characters) before following the next steps for building hardware bitstream.

From the Vivado welcome screen, in TCL console, run following commands
1. cd $ZYNQ_TRD_HOME/hardware/vivado
2. source ./scripts/project.tcl


The above step creates a project 'zynq_base_trd_2014.4'.

In the Flow Navigator pane on the left-hand side under Program and Debug, click Generate Bitstream. The bitstream will be generated at $ZYNQ_TRD_HOME/hardware/vivado/project/zynq_base_trd_2014.4.runs/impl_1/system_top_wrapper.bit


Exporting the Hardware Platform to XSDK

3.2 Steps for exporting the hardware platform to XSDK



From the Vivado menu bar, select File > Export > Export Hardware

In the Export Hardware window press OK. The SDK hardware platform will be exported to $ZYNQ_TRD_HOME/hardware/vivado/project/zynq_base_trd_2014.4.sdk/



4 Vivado HLS

Vivado HLS Flow for generating Sobel filter Vivado IP
Vivado HLS provides a tool and methodology for migrating algorithms coded in C, C++ or System-C from the Zynq PS onto the PL by generating RTL code.
The Sobel filter IP core used in the Zynq Base TRD was generated using this approach.
Pre-generated Sobel IP core is available at $ZYNQ_TRD_HOME/hardware/vivado/srcs/ip/xilinx_com_hls_image_filter_1_0/

To generate the Sobel filter Vivado IP, navigate to $ZYNQ_TRD_HOME/hardware/vivado_hls/sobel and run:

bash> vivado_hls -f run.tcl

The IP is located in the directory $ZYNQ_TRD_HOME/hardware/vivado_hls/prj/solution1/impl/ip/xilinx_com_hls_sobel_filter_1_0.zip
To use this IP and generate bitstream, replace the content of $ZYNQ_TRD_HOME/hardware/vivado/src/ip/xilinx_com_hls_image_filter_v1_0/ by content of the zip file generated by Vivado HLS tool.
And follow the steps in section 3.1 'Generating the bitstream'
To open the generated project in GUI mode, run: