Solution Zynq PL Programming With FPGA Manager

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Last updated: Nov 18, 2024 by Manne, Nava kishore

Table of Contents

Introduction‍

The information on this page is specific to Zynq-7000 SoC devices.  The Zynq-7000 Programmable Logic (PL) can be programmed either using First Stage Boot-loader (FSBL), U-Boot or through Linux.
This page provides the details about programming the PL from Linux world.

References:
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/driver-api/fpga

HW IP Features

  • Full-Bitstream and partial Bitstream loading.
  • Encrypted and Authenticated Bitstream loading.

Features supported in the Driver

  • Full-Bitstream Bitstream loading.
  • Encypted Bistream loading with Device-Key
 

Missing Features, Known Issues and Limitations

  • No support for partial Bitstream loading.
  • No support for Authenticated and Encrypted Bitstream loading.
  • It supports loading only .bin format files into the PL. These .bin files must be created using Bootgen and no other file formats are supported. Refer to this link for steps to generate a .bin file from a .bit file.
  • The existing Overlay fame-work allows the removal of overlay' only if it's the top-most one. So please follow the LIFO order to remove overlays from live tree.

NOTE:
The descriptions in subsequent sections refer to use of Device Tree Overlay (DTO) fragments with FPGA manager framework. It has to be noted that the generation of DTO fragments are not supported in official Xilinx Petalinux release. 
Below sections describe steps for manual creation of pl.dtsi (contains the DTO fragment) to be used along with Xilinx 2018.3 Linux.

Kernel Configuration

The following config options should be enabled in order to use FPGA Manager (In zynq_defconfig this options are enabled by default)

Zynq FPGA Manager Configuration:
Select: Device Drivers ---> FPGA Configuration Framework



DT overlay ConfigFS interface Configurati