Zynq UltraScale+ MPSoC VCU TRD 2021.1 - 10G HDMI Video Capture and Display
This page provides all the information related to Design Module 4 - VCU TRD 10G HDMI Video Capture and Display design.
Table of Contents
1 Overview
The primary goal of this Design is to demonstrate the capabilities of VCU hard block present in Zynq UltraScale+ EV devices. The TRD will serve as a platform to tune the performance parameters of VCU and arrive at optimal configurations for encoder and decoder blocks with the streaming use case where bandwidth plays a vital role. 10G will give sufficient bandwidth for the streaming protocol to play video pipeline smoothly.
This design supports the following video interfaces:
Sources:
HDMI-Rx capture pipeline implemented in the PL
File source (SD card, USB storage, SATA hard disk)
Stream-In from network or internet
Sinks:
HDMI-Tx display pipeline implemented in the PL
VCU Codec:
Video Encode/Decode capability using VCU hard block in PL
AVC/HEVC encoding
Encoder/decoder parameter configuration
Streaming Interfaces:
10G Ethernet on PL
1G Ethernet on PS
Video format:
NV12
10G Deliverables:
Pipeline | Input Source | Output Type | Resolution | Video Codec Type | Deliverables |
Record / Stream-Out pipeline | HDMI-Rx | File Sink / Stream-Out | 4K /1080p | HEVC / AVC | HDMI-Rx Video encodes with VCU and stores it in a container format |
Playback pipeline | File Source / Stream-In | HDMI-Tx | 4K /1080p | HEVC / AVC | Playback of the local-file / stream-in with video decoded using VCU and display on HDMI-Tx |
Capture → Display | HDMI-Rx | HDMI-Tx | 4K /1080p | HEVC / AVC | HDMI-Rx Video passes to HDMI-Tx without VCU |
Capture → Encode → Decode → Display | HDMI-Rx | HDMI-Tx | 4K /1080p | HEVC / AVC | HDMI-Rx raw video passes through VCU elements encoder and decoder and finally displays on HDMI-Tx |
Supported Resolution:
The table below provides the supported resolution in this design.
Resolution | Command Line | |
Single Stream | Multi-stream | |
4Kp60 | √ | NA |
4Kp30 | √ | NA |
1080p60 | √ | NA |
√ - Supported
NA – Not applicable
The below sections describe the 10G HDMI Video Capture and HDMI Display design. It is VCU TRD design supporting 10G HDMI-Rx and HDMI-Tx. For the overview, software tools, system requirements and design files follow the link below:
The below figure shows the 10G HDMI Video Capture and HDMI Display design hardware block diagram.
The below figure shows the 10G HDMI Video Capture and HDMI Display design software block diagram.
1.1 Board Setup
Refer below link for Board Setup
Board Connections:
The figure shows the ZCU106 board connections for 10G HDMI-Rx and HDMI-Tx Streaming support
1.2 Run Flow
The TRD package is released with the source code, Vivado project, Petalinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as TRD_HOME
which is the home directory.
Refer below link to download all TRD contents.
Refer Section 4.1 : Download the TRD of
Zynq UltraScale+ MPSoC VCU TRD 2021.1
wiki page to download all TRD contents.
TRD package contents are placed in the following directory structure. The user needs to copy all the files from the $TRD_HOME/images/vcu_10g/
to FAT32 formatted SD card directory.
rdf0428-zcu106-vcu-trd-2021-1/
├── apu
│ └── vcu_petalinux_bsp
├── images
│ ├── vcu_10g
│ ├── vcu_audio
│ ├── vcu_llp2_hdmi_nv12
│ ├── vcu_llp2_hdmi_nv16
│ ├── vcu_llp2_hdmi_xv20
│ ├── vcu_llp2_sdi_xv20
│ ├── vcu_multistream_nv12
│ ├── vcu_pcie
│ ├── vcu_plddrv1_hdr10_hdmi
│ ├── vcu_plddrv2_hdr10_hdmi
│ └── vcu_sdi_xv20
├── pcie_host_package
│ ├── COPYING
│ ├── include
│ ├── LICENSE
│ ├── readme.txt
│ ├── RELEASE
│ ├── tests
│ ├── tools
│ └── xdma
├── pl
│ ├── constrs
│ ├── designs
│ ├── prebuild
│ ├── README.md
│ └── srcs