Zynq UltraScale+ MPSoC VCU TRD 2021.1 - PL DDR HLG SDI Audio Video Capture and Display
This page provides detailed information related to Design Module 2 - HLG SDI Video Capture and Display with PLDDR
Table of Contents
1 Overview
The primary goal of this Design is to demonstrate the capabilities of VCU hard block present in Zynq UltraScale+ EV devices. The TRD will serve as a platform to tune the performance parameters of VCU and arrive at optimal configurations for encoder and decoder blocks. It has also added an initial support of 8-channels audio.
This module enables the capture of the Hybrid Log Gamma(HLG) video from an SDI-Rx subsystem implemented in the PL. The Hybrid Log Gamma(HLG) video can be displayed through the SDI-Tx subsystem implemented in the PL. The module can stream-out and stream-in live captured video frames through an Ethernet interface. This module supports single-stream for XV20 pixel format. In this design, PL_DDR is used for decoding and PS_DDR for encoding so that DDR bandwidth would be enough to support high bandwidth VCU applications requiring simultaneous encoder and decoder operations and transcoding at 4k@60 FPS.
This module supports the Encoding-Decoding and Transmission of Hybrid Log Gamma(HLG) video along with backward compatible Standard Dynamic Range(SDR) for SDI. It provides the ability to encode a wide dynamic range, while still being compatible with the existing transmission standards in the standard dynamic range (SDR) region. This HLG format encodes t