/
Xilinx V4L2 DisplayPort 1.4 RX Subsystem Driver

Xilinx V4L2 DisplayPort 1.4 RX Subsystem Driver

Nov 11, 2025

The purpose of this page is to describe the Linux V4L2 driver for the Xilinx DisplayPort 1.4 RX Subsystem Soft IP for Zynq UltraScale+ MPSoC and for Versal.

Note: The content of this page is applicable for the 2022.1 release. A few steps for building the kernel or taking sources from Git might be different for previous releases before 2022.1.

Table of Contents

Introduction

The DisplayPort (DP) 1.4 Receiver Subsystem is a plug-in solution for serial digital video data reception in large Video systems of up to video resolutions of Full Ultra HD (FUHD) at 30 fps.

 

It has the dynamic support of BPC (Bits per pixel) and different color formats. DisplayPort ( DP) 1.4 core supports 4 data lanes and each lane supports dynamic data rate up to 8.1Gb/s. It is a feature-rich soft IP incorporating all the necessary logic to properly interface with PHY layers and provide DP decoding functionality. The subsystem is a hierarchical IP that bundles a collection of DP RX-related IP sub-cores and outputs them as a single IP. The subsystem outputs multi-pixel video to AXI4-Stream Protocol interface. Below is the block diagram of the DisplayPort 1.4 Rx Subsystem.

 

Figure 1. Block diagram of the DisplayPort 1.4 Rx subsystem

DP Rx interface with Video PHY Controller for Zynq UltraScale+ MPSoC

 

The DP 1.4 Receiver Subsystem is a MAC subsystem which works with a Video PHY Controller (PHY) to create a video connectivity system. The DP 1.4 Receiver Subsystem is tightly coupled with the Xilinx Video PHY Controller, which itself is independent and offers flexible architecture with multiple-protocol support. Both the MAC and PHY are dynamically programmable through the AXI4-Lite interface.

Linux driver mentioned in this page only supports GTHE4 transreceiver.

Figure 2. Block diagram of MAC interface with PHY for Zynq

DP Rx interface with GT Quad base Controller for Versal

The DP 1.4 Receiver Subsystem is a MAC subsystem which works with a GT Quad Base Controller (PHY) to create a video connectivity system. The DP 1.4 Receiver Subsystem is tightly coupled with the Xilinx PHY Controller, which itself is independent and offers flexible architecture with multiple-protocol support. Both the MAC and PHY are dynamically programmable through the AXI4-Lite interface.

Figure 3. Block diagram of MAC interface with PHY for Versal

 

Driver Overview

DP Rx is the first node in the capture pipeline. The Linux driver is implemented within the V4L2 framework and creates a subdev node ( /dev/v4l2-subdev* ) which can be used to query the DP IP core. The DP Rx driver provides an abstracted view of the feature set provided by each included sub-core. It dynamically manages the data and control flow through the processing elements, based on the input stream configuration detected at run time. The general description of V4L2 framework is documented here: v4l2-framework.txt.

The Xilinx DP Rx is tightly coupled with the Xilinx video PHY driver and manages the interaction with the PHY layer internally. The Xilinx VPhy driver is an integral part of the solution and is automatically pulled-in when Xilinx DP Rx driver is selected in the kernel configuration.

For Versal, The PHY (GT Quad Base) driver need to be selected in kernel configuration.

MCDP6000 Retimer driver callback implementation:

The Xilinx solution expects the use of the MCDP6000 Retimer along with the DisplayPort 1.4 RX Subsystem solution. MCDP6000 as a retimer provides better SI features. As a retimer, the MCDP6000 removes the random and ISI jitter from the video source. For the Xilinx DisplayPort,  MCDP6000 configuration is controlled through an I2C interface. For a DisplayPort 1.4 solution, the MCDP6000 retimer chip is present on the FMC card and the driver for this chip is developed as a part of FMC driver. 

Because the DisplayPort 1.4 Rx driver handles the required MCDP6000 configurations, DP 1.4 Rx driver needs register the callback functions of the FMC driver. These functions will be called from the DP 1.4 Rx Driver interrupt context. Below are driver and device tree changes to achieve this callback mechanism.

  • Add reference to the FMC node in the DP 1.4 RX Device tree node. Below is an example.

dp_rx_hier_0_v_dp_rxss1_0: v_dp_rxss1@a0040000 { clock-names = "s_axi_aclk", "rx_vid_clk", "m_axis_aclk_stream1", "rx_lnk_clk", "m_aud_axis_aclk"; clocks = <&zynqmp_clk 71>, <&zynqmp_clk 72>, <&zynqmp_clk 72>, <&misc_clk_1>, <&zynqmp_clk 71>; compatible = "xlnx,v-dp-rxss-3.0","xlnx,vid-edid-1.0"; interrupt-names = "dprxss_dp_irq"; interrupt-parent = <&gic>; interrupts = <0 89 4>; reg = <0x0 0xa0040000 0x0 0x40000>,<0x0 0xa0010000 0x0 0x10000>; reg-names = "dp_base", "edid_base"; xlnx,dp-retimer = <&xfmc>; ----------- ----------- ------------ };

  • Implement Retimer configuration structure in the DP 1.4 Rx driver

  • Assign the FMC driver private data pointer to the DP 1.4 Rx driver member pointer

  • The DP 1.4 Rx drive will use the xdprxss→retimer_prvdata pointer to call the FMC driver callbacks.  For more information, see DP 1.4 Rx Linux driver.

Driver Features

 

IP Feature

2020.2

2021.1       

2021.2

2022.1

2022.2

2023.1

2023.2

2024.1

2024.2

2025.1

2025.2

IP version 

3.0

3.0

3.0

3.0

3.1

3.1

3.1

3.1

3.1

3.1

3.1

eDP and iDP supported.

No

No

No

No

No

No

No

No

No

No

No

Supports AXI4-Stream, native video input interfaces

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Support for 2 pixels per sample

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Support color space for RGB, YUV 4:4:4, YUV 4:2:2

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Support AXI4-Stream Video output stream and
Native Video output stream

Axi-Stream Video Only

Axi-Stream Video Only

Axi-Stream Video Only

Axi-Stream Video Only

Axi-Stream Video Only

Axi-Stream Video Only

Axi-Stream Video Only

Axi-Stream Video Only

Axi-Stream Video Only

Axi-Stream Video Only

Axi-Stream Video Only

Support for 2 channel audio with 44/48 KHz sample rates.

No

No

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

 8, 10, 12, or 16 bit per color component

Supports 8,10 bpc only

Supports 8,10 bpc only

Supports 8,10 bpc only

Supports 8,10 bpc only

Supports 8,10 bpc only

Supports 8,10 bpc only

Supports 8,10 bpc only

Supports 8,10 bpc only

Supports 8,10 bpc only

Supports 8,10 bpc only

Supports 8,10 bpc only

Support for 16-bit GT width.

Yes 

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Support for HDCP in MST mode

No

No

No

No

No

No

No

No

No

No

No

Supported resolution up to 8k30

Yes 

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

420 Colorimetry

No

No

No

No

No

No

Yes

Yes

Yes

Yes

Yes

Support for interlaced video in AXI4-Stream Interface

No

No

No

No

No

Yes

Yes

Yes

Yes

Yes

Yes

Dual-pixel splitter in native video mode

No

No

No

No

No

No

No

No

No

No

No

Supports SDP packet for static HDR mode

No

No

No

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Supports HDCP 1.3 and HDCP 2.2 decryption in SST

No

No

No

No

Supports only HDCP 1x

Supports only HDCP 1x

Supports  HDCP 1x and HDCP 2x

Supports  HDCP 1x and HDCP 2x

Supports  HDCP 1x and HDCP 2x

Supports  HDCP 1x and HDCP 2x

Supports  HDCP 1x and HDCP 2x

Versal Support

No

No

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

GTHE4 Support

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

GTYE5 Support

No

No

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Note: Versal family (vck90) linux Dp1.4 driver support was added on 2025.1 release onwards.

Missing Features / Known Issues / Limitations in Driver

  • This driver does not support the following features. 

    • MST

    • GTYE4

Kernel Configuration Options for Driver

  • Enable Xilinx DP Rx Subsystem driver

    • 2021.1 and onwards: the DisplayPort Rx driver is built as a part of the kernel, so enable the DisplayPort Rx driver in the kernel configuration. Run the below command from the PetaLinux project and select "Xilinx DP Rx Subsystem".

      $petalinux-config -c kernel

  • Enable Video PHY and FMC drivers

    • 2021.1 and onwards FMC driver is built as out-of-tree kernel module and therefore requires no kernel configuration. However, to enable the driver, the user must include it in the rootfs.

    • 2021.2 and onwards The Video phy controller driver is built as out-of-tree kernel module and therefore requires no kernel configuration. However to enable the driver, the user must include it in the rootfs. The following steps are required to enable the driver.

    • Make sure that the meta-user layer has the recipe-dp included. 

    • Add the recipe to the PetaLinux image. Edit project-spec/meta-user/conf/user-rootfsconfig and add the new recipe at the end:

      CONFIG_kernel-module-dp

    • Next include the driver in the rootfs

      $petalinux-config -c rootfs

    • Select "user-pakages->modules->kernel-module-dp", save and exit

  • Enable the GT QUAD base driver

    • 2022.1, the video phy driver for Versal systems is built as part of kernel., so enable this driver in the kernel configuration. Run the below command from the PetaLinux project and select "PHY_XILINX_DPGTQUAD".

      $petalinux-config -c kernel

  • Enable Audio drivers

    • 2022.1, the DP Rx driver supports audio and works with ALSA framework, Run the below command from the PetaLinux project and select "CONFIG_SND_SOC".

      $petalinux-config -c kernel

  • Build the project

    $petalinux-build

Device Tree Binding

The dts node should be defined with correct hardware configuration. An example device tree node is documented in 

2020.2 : https://github.com/XilinxDocumentation/devicetree/bindings/media/xilinx/xlnx,v-dprxss.yaml - Deprecated 

2021.1 : Documentation/devicetree/bindings/media/xilinx/xlnx,v-dprxss.yaml - Deprecated 

2021.2 : Documentation/devicetree/bindings/media/xilinx/xlnx,v-dprxss.yaml - Deprecated 

2022.1 :  Documentation/devicetree/bindings/media/xilinx/xlnx,v-dprxss.yaml

2023.2 : Documentation/devicetree/bindings/media/xilinx/xlnx,v-dprxss.yaml

2024.1 : Documentation/devicetree/bindings/media/xilinx/xlnx,v-dprxss.yaml

2024.2 : Documentation/devicetree/bindings/media/xilinx/xlnx,v-dprxss.yaml

2025.1 : Documentation/devicetree/bindings/media/xilinx/xlnx,v-dprxss.yaml

Building Device Tree with FMC

The below modifications to be done in the device-tree for FMC driver. 

Building Driver Modules in OSL flow

Note: The below steps are applicable for building images for 2020.1. These steps are deprecated. Customers are advised to use 2022.1 onwards drivers and the device tree.