Table of Contents

1 Overview

The primary goal of this Design is to demonstrate the capabilities of VCU hard block present in Zynq UltraScale+ EV devices. The TRD will serve as a platform to tune the performance parameters of VCU and arrive at optimal configurations for encoder and decoder blocks with the streaming use case where bandwidth plays a vital role. 

This design supports the following video interfaces:

Sources:

• File source (SD card, USB storage, SATA hard disk).
• Stream-In from network or internet.

Sinks:

• SDI-Tx display pipeline implemented in the PL.

VCU Codec:

• Video Encode/Decode capability using VCU hard block in PL 
  • AVC/HEVC encoding.
  • Encoder/decoder parameter configuration.

Streaming Interfaces:

• 1G Ethernet on PS

VIdeo format:

• XV20

Supported Features:

The table below provides the supported encoder feature in this release.

√ - Supported
NA – Not applicable
x – Not supported

Deliverables:

The below figure shows the SDI Video Display design hardware block diagram.

The below figure shows the SDI Video Display design software block diagram.

1.1 Board Setup

Refer below link for Board Setup

• Zynq UltraScale+ MPSoC VCU TRD 2019.1 Board Setup

1.2 Run Flow

The TRD package is released with the source code, Vivado project, Petalinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.

Refer below link to download all TRD contents.

• Zynq UltraScale+ MPSoC VCU TRD 2019.1 Download zip 

TRD package contents specific to SDI