Solution Zynq PL Programming

Table of Contents

Note: xilinx_devcfg.c driver got deprecated in 2018.1 release. Use ZYNQ FPGA manager to program Bit-stream into Zynq PL
Introduction
HW IP Features
Features supported in driver
Known Issues and Limitations
Kernel Configuration
Devicetree
Task Dependencies (Pre-requisites)
Tools Required
Input Files Required
Test procedure
Programming ZYNQ PL through Linux
Programming the PL through U-Boot
Expected Output
Mainline Status
Change Log
Related Links

Note: xilinx_devcfg.c driver got deprecated in 2018.1 release. Use ZYNQ FPGA manager to program Bit-stream into Zynq PL


http://www.wiki.xilinx.com/Solution+Zynq+PL+Programming+With+FPGA+Manager

Introduction

The Zynq Programmable Logic (PL) can be programmed by the First Stage Bootloader (FSBL), U-Boot or through Linux. Programming the PL at different stages may be advantageous for different projects and workflows.

HW IP Features


Features supported in driver


Known Issues and Limitations


Kernel Configuration

Device Drivers ---> Character devices ---> <*> Xilinx Device Configuration



Devicetree

devcfg: devcfg@f8007000 {
                        compatible = "xlnx,zynq-devcfg-1.0";
                        interrupt-parent = <&&intc>;
                        interrupts = <0 8 4>;
                        reg = <0xf8007000 0x100>;
                        clocks = <&&clkc 12>, <&&clkc 15>, <&&clkc 16>, <&&clkc 17>, <&&clkc 18>;
                        clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
                        syscon = <&&slcr>;
                };

Task Dependencies (Pre-requisites)



Tools Required


Input Files Required




Test procedure

Programming ZYNQ PL through Linux

Once booted into Linux, write the bitstream file to the devcfg device:
$cat bitstream.bit > /dev/xdevcfg
Programming the PL through the FSBL
The First Stage Boot-Loader (FSBL) is capable of programming the PL before loading U-Boot, which may be necessary for some applications. To have the FSBL load the PL, include the bitstream file when generating boot.bin and boot normally.
References:

Programming the PL through U-Boot

Load the bitstream into memory and then use fpga loadb to program the PL; for example:
U-Boot> fatload mmc 0 0x4000000 bitstream.bit
U-Boot> fpga loadb 0 0x4000000 <bitstream file size>

Expected Output

Linux:
After, the prog_done file should indicate that the programming was successful.
$ cat /sys/class/xdevcfg/xdevcfg/device/prog_done
1

Mainline Status


Change Log

2016.3
Summary:
Commits:

2016.4

2017.1
Summary:
Commits:

2017.2

2017.3
Summary:
Commits:

2017.4
Summary:
Commits:

Related Links