Reading PHY registers over MDIO via the PHY Management GEM Register

Owned by stephenm
Last updated: Dec 09, 2020 by William Cassells
4 min read

In this simple demo, we will see how to manually read the PHY registers over MDIO. For ease of use, users should use utilities such as mii dump in u-boot or similar in Linux too. However, the flow below shows how this can be done simply via devmem incase such utilities are unavailable. There is also a section on how to read extended register over xsct.


PHY Management Register:

The PHY management register can be seen below. Users can view this in the Zynq Ultrascale register reference here. We shall use this to access the PHY registers.

Management Port Enable bit:

User will first need to enable the Management port:


Using devmem to read the PHY registers:

ifconfig eth0 down

Users will need to bring the link down first. For example,  ifconfig eth0 down

Boot linux, and use devmem to enable the management port in the Network config for the GEM3

man port en
devmem 0xff0e0000 32 0x00000010

gem addresses

The respective GEM Network control register addresses are; GEM2 = 0xff0d0000, GEM1 = 0xff0c0000, GEM0 = 0xff0b0000


To create the PHY read command:

phy man
0110<phy addr><phy reg>100000000000000000

Where the phy addr is 5 bits, and the phy reg is 5 bits

So, if users want to read the BMCR (0x00, or 00000) on the PHY connected to GEM 3 (phy address 0x0c, or 01100)

phy man read
0110 0110 0000 0010 0000 0000 0000 0000 = 66020000hex

So, the command would be:

phy man read
devmem 0xff0e0034 32 0x66020000
devmem 0xff0e0034

gem addresses

The respective GEM PHY Management addresses are; GEM2 = 0xff0d0034, GEM1 = 0xff0c0034, GEM0 = 0xff0b0034

For example, this will result in:

So, the result is the first 15 bits; 1140

phy addr

Note: if the result here is 0xffffffff then the phy addr is most likely incorrect


This can be correlated in the TI datasheet (the PHY on the ZCU102 board):


As a sanity check, users should read the PHY ID (0x2, and 0x3):

So, here 0x02 = 2000, and 0x3 = 0xa231 which is expected for my TI PHY


Writing to Extended Registers:

As you would have noticed, the register address field is 5 bits. So, only phy addresses from 0x0 to 0x1f can be accessed.

To access other registers, for example the bootstrap register. Then users would need to use the Extended Address register.

On the TI phy used on the ZCU102, this can be seen below:

These instructions mirror, the ones in the TI PHY datasheet page 39

So, first we need to write the value 0x001f to PHY register REGCR (or 0x0d). Our PHY Addr is 0x0c

  • 0101 <PHY Addr> <PHY Register>10 0000 0000 0001 1111
  • 0101 <01100> <01101>10 0000 0000 0001 1111
  • 0101 0110 0011 0110 0000 0000 0001 1111
  • mwr 0xff0e0034 0x5636001f

Write the Bootstrap config register (0x6e) to the ADDAR (0x0e). Our PHY Addr is 0x0c

  • 0101 <PHY Addr> <PHY Register>10 0000 0000 0110 1110
  • 0101 <01100> <01110>10 0000 0000 0110 1110
  • 0101 0110 0011 1010 0000 0000 0110 1110
  • mwr 0xff0e0034 0x563a006e

Write the value (0x401f) to the REGCR (0x0d). Our PHY Addr is 0x0c

  • 0101 <PHY Addr> <PHY Register>10 0100 0000 0001 1111
  • 0101 <01100> <01101>10 0100 0000 0001 1111
  • 0101 0110 0011 0110 0100 0000 0001 1111
  • mwr 0xff0e0034 0x5636401f

Read the content of the desired extended register ADDAR (0x0e). Our PHY Addr is 0x0c

  • 0110 <PHY Addr> <PHY Register>10 0000 0000 0000 0000
  • 0110 <01100> <01110>10 0100 0000 0000 0000
  • 0110 0110 0011 1010 0000 0000 0000 0000
  • mwr 0xff0e0034 0x663a0000


For example:

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