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#ifdef XFSBL_PS_DDR
#ifdef XPAR_DYNAMIC_DDR_ENABLED
	/*
	 * This function is used for all the ZynqMP boards.
	 * This function initialize the DDR by fetching the SPD data from
	 * EEPROM. This function will determine the type of the DDR and decode
	 * the SPD structure accordingly. The SPD data is used to calculate the
	 * register values of DDR controller and DDR PHY.
	 */
//	Status = XFsbl_DdrInit();
//	if (XFSBL_SUCCESS != Status) {
//		XFsbl_Printf(DEBUG_GENERAL,"XFSBL_DDR_INIT_FAILED\n\r");
//		goto END;
//	}
#endif
#endif

Unable to see ARM-R5 CPUs on Zynq UltraScale+ MPSoC and

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Versal Adaptive SoC platforms with XSDB on 2020.1 QEMU

2020.1 QEMU does not give processor information to XSDB, so XSDB does not know that these platforms have R5s on them.

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AR link: https://xilinx.sharepoint.com/sites/XKB/SitePages/Articleviewer.aspx?ArticleNumber=75599

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Versal Adaptive SoC LPD XPPU Is not controlling APU accesses to TCM

On hardware, LPD XPPU can control accesses to TCM, however this behavior is not implemented in QEMU.
This is due to how the XPPU is implemented in QEMU, and the possibility of LPD XPPU blocking APU and RPU accesses to TCM.

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