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Xilinx exposes a SystemC/TLM interface to connect QEMU, which models the hardened Processing System (PS) of any Zynq-based or Versal ACAP Versal Adaptive SoC product, to a model of your own IP instantiated in the Programmable Logic (PL).
Your IP must be written in either Verilog or SystemC.
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libSystemCTLM-SoC provides a standard SystemC wrapper around Zynq7000, Zynq Ultrascale+ MPSoC, and Versal ACAP Versal Adaptive SoC hardened PS (as seen in the right hand side of Figure 1), enabling integrators to connect various IP models just like any other SystemC compatible modeling environment.
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| Platform | sync-quantum | icount (optional) |
|---|---|---|
| Zynq UltraScale+ MPSoC | 1000000 | 1 |
| Versal ACAPAdaptive SoC | 1000000 | 1 |
| Zynq - 7000 | 100000 | 7 |
Example QEMU Command
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