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The Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable. This enabled enables a user to access a Xilinx device through another medium (In this case we use Ethernet) instead of needing a dedicated JTAG cable. This can be advantageous for in-field debugging or during stress test scenarios where JTAG is not an option.
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The Debug Bridge must be configured for the AXI to BSCAN mode since the CPU will be driving the Debug Bridge IP based on packets received from the network; which ultimately need access to the device’s Boundary Scan. If the SoC were to drive another FPGA via JTAG pins, then the AXI to JTAG mode would be used. In our demonstration, the configuration of the Debug Bridge should be as shown in the following illustration.
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Software
The Xilinx Virtual Cable GitHub project XilinxVirtualCable provides the source code for a Linux kernel driver and Linux application. This wiki page gives details using PetaLinux but it could be accomplished in other manners as PetaLinux is only the build mechanism.
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The xvc-driver module recipe you created can be found in the <plnx-proj-root>/project-spec/meta-user/recipes-modules/xvc-driver directory, . Copy some of the source code files from the XilinxVirtualCable repository, including the xvc_driver*.c, xvc_driver.h, xvc_user_config.h, and xvc_ioctl.h, into the recipe to build the kernel module in the PetaLinux project (<plnx-proj-root>/project-spec/meta-user/recipes-modules/xvc-driver/files).
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Not all the source files are required.
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#if KERNEL_VERSION(5, 4, 0) >= LINUX_VERSION_CODE
mmiowb();
#endif
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PetaLinux Application
Create an application in PetaLinux.
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