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Table of Contents
2 Introduction...
Table of Contents
| Table of Contents | ||
|---|---|---|
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1 Revision History
This wiki page complements the 2018.3 version of the Software Acceleration TRD. For other versions, refer to the Zynq UltraScale+ MPSoC Software Acceleration TRD overview page.
Change Log:
- Updated all projects, IPs, and tools versions to 2018.3
2 Introduction
This wiki page contains information on how to build various components of the Zynq UltraScale+ MPSoC Software Acceleration Targeted Reference Design (TRD), version 2018.3. The page also has the information on how to set-up the hardware and software platforms and run the design using the ZCU102 evaluation kit (Rev 1.0 with production silicon).
3 About the TRD
The Software Acceleration TRD is an embedded signal processing application designed to showcase various features and capabilities of the Zynq UltraScale+ MPSoC ZU9EG device for the embedded domain. The TRD consists of two elements: The Zynq UltraScale+ MPSoC Processing System (PS) and a signal processing application implemented in Programmable Logic (PL). The MPSoC allows you to implement a signal processing algorithm that performs Fast Fourier Transform (FFT) on samples (coming from Test Pattern Generator (TPG) in Application Processing Unit (APU) or System Monitoring (SYSMON) through an external channel either as a software program running on the Zynq UltraScale+ MPSoC based PS or as a hardware accelerator inside the PL. The design has three accelerator cores generated using SDx for computing 4096, 16384, and 65536 point FFTs. The data transfers of the SDx accelerators is controlled by the APU. There is one accelerator (FFT IP from the Vivado IP catalog) for 4096 point FFT controlled by the Real-Time Processing Unit (RPU). The TRD demonstrates how to seamlessly switch between a software or a hardware implementation and to evaluate the cost and benefit of each implementation. The TRD also demonstrates the value of offloading computation-intensive tasks onto PL, thereby freeing the CPU resources to be available for user-specific applications.
For detailed information on the complete feature set, or hardware and software architecture of the design, please refer to the TRD user guide UG1211.
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- From the welcome screen, click Create Library Project. Enter "fft" as Project Name. Click Next.
- Select Accelerated Library Type as "Shared Library". Click Next.
- Click + symbol to add Custom Platform, browse to the $TRD_HOME/apu/zcu102_swaccel_trd folder and click OK. Select the "zcu102_swaccel_trd [custom]" platform from the list and click 'Next'.
- Click Next in System Configuration window.
- Select FFT Library from the template list and click Finish.
- In the "SDx Application Project Settings" panel, change the active build configuration to "Release" which will have the pre-selected Hardware Function marked for acceleration. Make sure the 'Generate SD card image' box is checked.
- Right-click on the fft project and select Build Project.
- Copy the content of the generated sd_card folder to the images.
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