This page describes tips to help with an isolation flow on Versalimprove R5 data abort exceptions for isolation use cases.

Table of Contents

Introduction

A data abort exception occurs when the CPU attempts to access (read or write) an address that is not supported for some reason such as the PL not being loaded or an isolation flow. For most designs this is not an issue as it’s typically a design flaw that is found during early testing and does not occur during normal operation. The concepts of this page apply to all the SoC CPUs but the R5 with bare metal is illustrated as the Cortex A CPUs typically run Linux such that changing exception handling is more complex and untypical.

Isolation Flow

Isolation allows specific memory ranges to be allowed by some AXI masters and denied to others. This page provides tips to help deal with isolation.

R5 Isolation Denial

The manner by which addresses are denied Default denial of addresses in Versal has changed from MPSoC. On Versal an access to an isolated address that is denied causes a data abort to the AXI master. Read and write operations behave differently with read operations being more catastrophic to the application. A read operation causes the read to be retried infinitely while a write operation does not. Users may want to deal with the data abort in a graceful manner to continue operating. This paragraph illustrates the minor changes to allow the R5 detect the denial and continue operating. This prototype was built and tested with Vitis 2022.2 on a VCK190 board.

Data Abort Exception

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Details

By default the AMD/Xilinx Standalone (bare metal) BSP handles a data abort for a read operation and then returns to the same data access in the application causing it to be retried indefinitely.

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