- This page gives an overview of the bare-metal driver support for the Xilinx® LogiCORE™ IP AXI
- Video Direct Memory Access (AXI VDMA)soft IP.
Table of Contents
Table of Contents
exclude Table of Contents Introduction
The
AXI VDMA core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. It provides high-bandwidth direct Memory access between memory and AXI4-Stream video type target peripherals including peripherals which support the AXI4-Stream Video protocol as described in the Video IP:AXI Feature Adoption section of the Vivado AXI Reference Guide (UG1037)
For more information, please refer to the AXI VDMA product page which includes links to the official documentation and resource utilization.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
<If there are multiple drivers supporting this IP, we should make that statement here and add to the table>
Driver Name Path in Vitis Path in Github axivdma <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/axivdma_<version> https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axivdma
Driver
Info Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/axivdma
The driver source code is organized into different folders.
The table below shows the axivdma driver source organization
AXI VDMA
├── doc:
.
Directory Description doc Provides the API and data structure details
data
Driver .tcl and
.
mdd file
examples Example applications that show how to use the driver
features
src Driver source files
Controller Features
- AXI4 Compliant
- Primary AXI4 data width support of 32, 64, 128, 256, 512, and 1,024 bits
- Primary AXI4-Stream data width support of multiples of 8 up to 1,024 bits
- Optional Data Realignment Engine
- Optional Genlock Synchronization
- Independent, asynchronous channel operation
- Dynamic clock frequency change of AXI4-Stream interface clocks
- Optional frame advance or repeat on error
- Supports up to 32 frame buffers
- Supports up to 64-bit address space
Driver Implementation
For a full list of features supported by this IP, please refer to the AXI VDMA product page.
Features
The AXI VDMA Standalone driver supports the
- following features:
- Supports 64-bit Addressing
- Supports Gen-Lock Synchronization
- Supports up to 32 frame buffers
- Supports frame advance or repeat on error
- Supports Parking Mode
- Supports Circular Buffer Mode
Test cases
- Refer below pah for testing different examples for each feature of the IP.
Known Issues and Limitations
The following is a list of known limitations of the driver and features of the IP that are not currently implemented:
- When H/w is configured without DRE driver will throw an error if the user sends an unaligned buffer address.
- User application should handle buffer address alignment in case h/w is configured without DRE
Example Design Architecture
The examples assumes AXI VDMA IP is configured in loopback mode.
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axivdma/examples
Test Name Example Source Description Self Test xaxivdma_example_selftest.c
This example does a basic reset of the core and checks core is coming out of reset or not. Video Frame transfer with interrupts xaxivdma_example_intr.c
This example demonstrates how to
vdma.c and vdma_api.c : This example demonstrates how to use triple frame buffer feature in the AXI Video DMA
Known issues and Limitations
- When H/w is configured without DRE driver will throw an error if the user sends an unaligned buffer address.
- User application should handle buffer address alignment in case h/w is configured without DRE
Change Log
2020.2
- Consolidate debug header files.
- Support parallel make execution.
- Read frame store from user-defined config parameter.
- In example add frame data check support.
257c0d9e3742 BSP: Consolidate and add the drivers xdebug.h data to common xdebug.h
4dc85994d6fb Makefile: Remove realpath command
5736883911ba axivdma: Update Makefile to support parallel make execution
a24706fde355 axivdma: Add workaround to fix the mismatch of frame store value
1bed2b805d3a axivdma: Revert to fix the compilation failure
e6b652880478 axivdma: Make Exiting main as the last print
2639f23b02b1 axivdma: To add frame data check support
0b19e93d8617 axivdma: Fix to read frame store from user-defined config parameter
- Fix xaxivdma_example_intr example failure in release mode
- Clean up old versions for axivdma driver
ca4088c axivdma: Fix xaxivdma_example_intr example failure in release mode
fef351c axivdma: Clean up old versions for axivdma driver
- None
- None
- Add vertical programming support.
Commit Id's
9b66e32 examples: Set vertical flip default state
81b08c0 Enable VDMA S2MM vertical flip support
- None
- Fix compilation error in selftest example
- Align default TX/RX framebuffer count with IP configuration
63368d9 vdma: Align default TX/RX framebuffer count with IP configuration
a3d2180 axivdma: Fix compilation error in selftest example
2017.4
- None
- None
- None
- Fixed compilation errors in the driver when compiled the driver with C++ compiler
- Modified text file to generate doxygen for examples
578c86f : Fixed compilation errors in the driver when compiled the driver with C++ compiler
e9b7aed : Modified text file to generate doxygen for examples
do video frame transfers in AXI Video DMA loopback mode. This example reads video frames from memory, using Memory Map to Stream (MM2S) interface, and then video frames are written to memory using Stream to Memory Map (S2MM) AXI4 interface. At the end of transfer it does sanity check and report pass/fail status. Example Application Usage
Self Test
This example does a basic reset of the core and checks core is coming out of reset or not.
Expected Output
Code Block theme Midnight --- Entering main() --- Successfully ran AxiVDMASelfTest Example --- Exiting main() ---
Video Frame transfer with interrupts
This example demonstrates how to do video frame transfers in AXI Video DMA loopback mode.
Expected Output
Code Block theme Midnight --- Entering main() --- Successfully ran axivdma intr Example --- Exiting main() ---
Change Log
2021.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L43
2020.2
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L358
2020.1
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L290
2019.2
None
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