Table of Contents

Introduction

...

• 2021.1 release on-wards Linux Arasan NAND driver uses the SW-ECC with BCH as the default ECC detection/correction, this results in a degradation of performance as compared to HW-ECC. -  AR-76631
• 2021.x, 2022.x, 2023.1 BBT of NAND is different between U-boot and Linux kernel AR-Link

Bad Block management

Bad block management implementation is same as Linux MTD bad block management with the exception of reserving number of blocks to store Bad Block Table (BBT) from default 4 blocks to 64 blocks. This is because one of the Micron flash part MT29F32G08ABCDB has last 32 blocks as bad most of the times. Since it was difficult to store bad block table in last 4 blocks, the number of blocks are increased to 64 blocks.

...

config MTD_NAND_ECC_SW_BCH
        bool "Support software BCH ECC"
        select BCH
        default n
        help
          This enables support for software BCH error correction. Binary BCH
          codes are more powerful and cpu intensive than traditional Hamming
          ECC codes. They are used with NAND devices requiring more than 1 bit
          of error correction.

config MTD_NAND_ARASAN
    tristate "Support for Arasan Nand Flash controller"
    depends on HAS_IOMEM && HAS_DMA
	select BCH
    help
      Enables the driver for the Arasan NAND flash controller on Zynq Ultrascale+ MPSoC.

Device Tree Settings

More information on nand device tree node details, refer the link Nand device tree
Example for device tree

...

Below test cases requires the following user space tools
mtd_debug, nandtest
All these tools are part of the mtd-utils and source is available from link http://git.infradead.org/mtd-utils.git

Note: expected output may not be same and its all depends on the flash device and configuration of the target system.

...

• 2016.3

  • Summary
    • Added runtime clock gating support
    • Fix the chip select/de select order to aid the runtime clock gating support
  • Commits
    • a629532 nand: arasan: Add runtime support
    • 314921f nand: arasan: balance the select and deselect

• 2016.4

  • Summary
    • None
  • Commits
    • None

• 2017.1

  • Summary
    • Update Arasan Nand flash controller as per latest kernel change
    • Change ref clk in SDR modes 2 to 5 to less than 90MHz
  • Commits
    • 6c59929: Update Arasan Nand flash controller driver
    • cab8221: Change ref clk in SDR modes 2 to 5

• 2017.2

  • Summary
    • Add on-die ecc support
    • Use nand helpers to correct bit flips in the data
  • Commits
    • 59440b6 Add on-die ecc support
    • 6216d9d2 Add nand helper functions to correct data bitflips

• 2017.3

  • Summary
    • Add 64bit dma support
    • Add runtime support
  • Commits
    • c66ee9bAdd 64bit dma support
    • 46b31a3 Add runtime support

• 2017.4

  • None

• 2018.1

  • None

• 2018.2

  • None

• 2018.3

  • Summary
    • Fix initialization of controller structure
  • Commits
    • 17c06e9 Fix initialization of controller structure

• 2019.1

  • Summary
    • Updated the driver to use →exec_op()
  • Commits:
    • d0674f0 Added support for →exec_op()

• 2019.2

  • Summary
    • Move interrupt completion at the end
  • Commits:
    • cf17190e Disable the interrupts and then signal the completion

• 2020.1

  • Summary
    • Nand driver update to use latest kernel NAND framework
    • Add on-die ecc support
  • Commits:
    • c63ef54e 
    • 6a8aa10

• 2020.2

  • Summary
    • None
  • Commits
    • None

• 2021.1

  • Summary
    • Support the hardware BCH ECC engine.
    • Use the ECC framework OOB layouts.
    • Add NV-DDR Interface support.
    • Workaround a misbehaving prog type with NV-DDR.
  • Commits
    • 88ffef1
    • 1e3b37a
    • 12f5395
    • e47d5c6

• 2021.2

  • Summary
    • Add a helper to check if a CHANGE_READ_COLUMN is possible.
    • Check if CHANGE_READ_COLUMN is supported.
  • Commits
    • e2ebc05
    • 4ef7aa1

• 2022.1

  • Summary
    • Prevent an unsupported configuration
  • Commits
    • f752d78

• 2022.2

  • Summary
    • Update NAND bus clock instead of system clock
    • Fix clock rate in NV-DDR
    • Provide an additional ->exec_op() check
  • Commits
    • 7a283ad
    • 209d879
    • 6ced49c

• 2023.1

  • Summary
    • Update NAND bus clock instead of system clock
    • Fix clock rate in NV-DDR
  • Commits
    • 7499bfe
    • e16ecee

• 2023.2

  • Summary
    • Avoid overwriting valid data while checking for bitflips during HW-ECC read
  • Commits
    • 9a5cf26

Mainline status

Mainlined

Related Links

...