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Introduction

Revision History

This wiki page complements the 2017.2 version of the Software Acceleration TRD. For other versions, refer to the Zynq UltraScale+ MPSoC Software Acceleration TRD overview page.

Change Log:

  • Update all projects, IPs, and tools versions to 2017.2
  • Remove hard-TPG from design
  • Use SDSoC based function instead of linux based function to measure performance.
  • Move NE10 headers and library to platform.
  • Performance improvement in all computation engines, especifically in RPU as Coproc (~1100us -> ~800us) and APU-PL (~120us -> ~70us)
  • Simplified build-steps for better user-experience
  • Various fixes and clean-up

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