This page covers the Linux driver for the Xilinx Soft DMA IPs, including AXI DMA, AXI CDMA, AXI MCMDA and AXI VDMA for Zynq, Zynq Ultrascale+ MPSoC, Versal and Microblaze.
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The test client can be configured as loadable or in-built kernel module.
Device-tree Node for the test client
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vdmatest_1: vdmatest@1 { compatible ="xlnx,axi-vdma-test-1.00.a"; xlnx,num-fstores = <0x3>; dmas = <&axi_vdma_0 0 &axi_vdma_0 1>; dma-names = "vdma0", "vdma1"; } ; |
Running the test client will display the message when the test is successful,
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vdmatest: Started 1 threads using dma0chan0 dma0chan1 dma0chan0-dma0c: terminating after 1 tests, 0 failures (status 0) |
Mainline Status
The current driver available in the Xilinx Linux git is in sync with the open source kernel driver except for the following- DMA Client driver (axidmatest and vdmatest - these are xilinx specific dma client driver and not streamable)
Change Log
2023.2
- Mainline fix pulled in to handle child node error path
Commitshttps://github.com/Xilinx/linux-xlnx/commits/xilinx-v2023.2/drivers/dma/xilinx/xilinx_dma.c
2023.1
- Error path handling and kernel doc fix
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- Remove axidma multi-channel mode support
- Fix 64-bit simple AXIDMA transfer
- Fix control reg update in vdma_channel_set_config
Commits:
8c8e3b1 dmaengine: xilinx_dma: Remove axidma multi-channel mode support
c3b6c45 dmaengine: xilinx_dma: Fix 64-bit simple AXIDMA transfer
965442b dmaengine: xilinx_dma: Introduce helper macro for preparing dma address
fbde9af dmaengine: xilinx_dma: Fix control reg update in vdma_channel_set_config
2018.3
- Reset DMA channel in dma_terminate_all.
- Fix 64-bit simple CDMA transfer.
- Code refactoring.
Commits:
1c8b3af dmaengine: xilinx_dma: Reset DMA channel in dma_terminate_all
cf9dfe6 dmaengine: xilinx_dma: Minor refactoring
44b796e dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer
113e03d dmaengine: xilinx_dma: Move enum xdma_ip_type to driver file
55ea663 dmaengine: xilinx_dma: Fix typos
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