Axi traffic generator

AXI Traffic generator Standalone Driver

Introduction
This page gives an overview of axi traffic generator driver which is available as part of the Xilinx Vivado and SDK distribution.
The Xilinx® LogiCORE™ IP AXI traffic generator core is a soft Xilinx IP core for
Use with the Xilinx Vivado® Design Suite.

Source Path for the driver
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/trafgen

Driver source code is organized into different folders. Below diagram shows the trafgen driver source organization

ATG
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files

HW IP features

• Flexible data width capability (32/64-bit) on output AXI4-memory map Slave, (32/64/
  128/256/512-bit) on output AXI4-memory map Master interface
• Flexible data width capability from 8-bit to 1,024-bit in multiples of eight output
• AXI4-stream Master/Slave interface
• Interrupt support for indicating completion for traffic generation.
• Error interrupt pin indicating error occurred during core operation. Error registers can
  be read to understand the error occurred.

Features supported in driver

The AXI Traffic generator Standalone driver support the below things.

• Flexible data width capability (32/64-bit) on output AXI4-memory map Slave, (32/64/
  128/256/512-bit) on output AXI4-memory map Master interface
• Flexible data width capability from 8-bit to 1,024-bit in multiples of eight output
• AXI4-stream Master/Slave interface
• Interrupt support for indicating completion for traffic generation.
• Error interrupt pin indicating error occurred during core operation. Error registers can
  be read to understand the error occurred.

Missing Features, Known Issues and Limitations

None

Test Procedure

Refer below path for testing different examples for each feature of the IP.
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/trafgen/examples
xtrafgen_interrupt_example.c : This example programs known data to master RAM and command to command ram and param ram. The data will
be taken from master RAM and programmed to the slave in interrupt mode.
xtrafgen_polling_example.c :
his example programs known data to master RAM and command to command ram and param ram. The data will
be taken from master RAM and programmed to the slave.
xtrafgen_static_mode_example.c : This example demonstrates how to use axi traffic generator in static mode.
xtrafgen_master_streaming_example.c : This example demonstrates how to use axi traffic generator in streaming mode.

Change Log

2017.1

• None

2017.2

• None

2017.3

• None

2017.4

• None

2018.1

• None

2018.2

• None

2018.3

• None

2019.1

• Summary:
  • Changes in Makefile to make map file consistent in windows & other platforms.
• Commits:
  • 2700c6b: Changes in Makefile to make map file consistent in windows & other platforms. 

2019.2

• None

2020.1

• None

2020.2

• Summary:
  • trafgen: Update Makefile for parallel make execution
  • Makefile: Remove realpath command
• Commits:
  • f9314b9: trafgen: Update Makefile for parallel make execution
  • 4dc8599: Makefile: Remove realpath command

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries