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  1. Content
  2. home
  3. Zynq UltraScale+ MPSoC
  4. Zynq UltraScale+ MPSoC Targeted Reference Designs (TRD)
  5. Zynq UltraScale MPSoC Software Acceleration TRD
  6. Zynq UltraScale MPSoC Software Acceleration TRD 2017.4

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Ben Levinsky

Ben Levinsky

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Sep 28, 2018

Oct 01, 2018

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Table of Contents

1 Revision History
2 Introduction
3 About the TRD
4 Download the TRD
5 TRD Directory Structure and Package Contents
6 Running the Demo
7 Hardware Setup Requirements
7.1 Requirements for the TRD demo setup:
8 Board Setup
9 Run QT GUI application
9.1 Powering on the QT-based GUI application demo
9.2 Running the Qt-based GUI application demo
9.2.1 Test Start/Pause
9.2.2 Input Source
9.2.3 FFT Computation Engine
9.2.4 FFT Length
9.2.5 FFT Window
9.2.6 Frequency Zoom
9.2.7 FFT Scale
9.2.8 Sample Rate
9.2.9 Time and Frequency domain plots
9.2.10 FFT Computation time plot
9.2.11 CPU Utilization plot
9.2.12 PS-PL Interface Performance plot
9.2.13 PL Die temperature
9.2.14 Block Diagram view
10 Building the Software components
10.1 Building RPU firmware using XSDK
10.2 Petalinux BSP
10.3 Build BitStream and FFT Shared Object using SDSoC
10.4 QT-application:
11 Support

1 Revision History


This wiki page complements the 2017.4 version of the Software Acceleration TRD. For other versions, refer to the Zynq UltraScale+ MPSoC Software Acceleration TRD overview page.

Change Log:
  • Updated all projects, IPs, and tools versions to 2017.4
  • Use dsa for hardware platform
  • Various fixes and clean-up

2 Introduction

...

General
Content
Integrations
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