ZynqMP DDRless System
This tech tip is indeed to explain how to setup a complete step by step a DDRless ZynqMP system, using the ZCU102 board.
Table of Contents
|Table of Contents|
Hardware PlatformCreate a Vivado 2016.4 project for ZCU102 board and a new BD design. Add a Zynq MPSoC block into the design and apply the preset configuration values using the "Run Block Automation" feature.
Double click into the MPSoC block and disable the DDR controller
Add a AXI GPIO block into the design and run the connection automation feature, connecting the GPIO interface to the board leds
Note: This is going to be used to test how the PL has been loaded in the device
Double click the GPIO block and modify the default data values to generate a visible pattern in the board LEDs
Validate the block design, save, create the HDL wrapper, generate the output products and the bitstream and export the project to the SDK.
Software PlatformCreate two standalone project using the ZynqMPSoC FSBL template and Hello_World template.
In order to get more information about the loading process enable the FSBL debug traces defining FSBL_DEBUG symbol in the fsbl project.
As both application must be loaded in the OCM memory, overlapping has to be avoided modifying the default linker scripts
The FSBL has been designed to load the applications in the last OCM bank, so modify the hello_world application linker script to locate the executable in that bank.
Regarding the bitstream loading process, as the OCM is not big enough to load the entire bitstream file, a chunking process is going to be used by default if the FSBL detects that only OCM is available.
Boot ImageOnce both applications has been generated the last step corresponds to create the boot image file using bootgen wizard (Xilinx Toolx -> Create Boot Image).
Create a new image with the following configuration (FSBL + Bitstream + Standalone app)
Load the BOOT.bin file in a SD card and run the evaluation board in SD boot mode to run the example.
Check both the serial port and the board LEDs to ensure that the PL has been programed in the FPGA side and that hello_world application has been loaded in the processor side.