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Zynq UltraScale+ MPSoC - 64-bit DDR access with ECCTable of Contents

Table of Contents

Document History

2018.1



DateVersionAuthorDescription of Revisions
02/22/20171.0Srikanth ErusalagandiInitial Version (2016.4)
05/22/21072.0Srikanth Erusalagandi2017.1
14/06/20182.1Surender Polsani2018.1

1. Summary


This technical article describes the implementation of an Error Correction Control (ECC) module in the Zynq UltraScale+ MPSoC DDR Controller. The reference design provided here detects and corrects all single bit errors (in a codeword consisting of either 64-bit data and 8 parity bits) , and it detects double bit errors in the data. This design utilizes Hamming code, a simple yet powerful method for ECC operations. As a result, this design offers exceptional performance and resource utilization.

2. Introduction


As technology is evolving, dynamic random-access memory (DRAM) device size increases and components on chips get smaller, due to that DRAM chips becoming more affected by electrical or magnetic interference. Lower energy particles are able to change memory cell’s state. These kinds of interferences can cause a single bit of DRAM to spontaneously flip to the opposite state. It can lead system to either crash or to corruption of data.
Several approaches have been developed to deal with unwanted bit-flips. One of the approaches is to calculate an error-correcting code (ECC) for data and store it in DRAM along with data. The most common ECC, a SECDED Hamming code, allow a single bit error to be corrected and double bit errors to be detected.
The Zynq UltraScale+ MPSoC offers 72-bit interface which includes 64bits bus for data and 8-bit bus for storing parity bits for calculating the ECC . This reference design targets the ZCU102 Evaluation board which has a 72-bit double data rate SODIMM memory (Kingston KVR21SE15S8/4) on board allowing you to access the complete 4GB of RAM available on the board.

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