Versions Compared


  • This line was added.
  • This line was removed.
  • Formatting was changed.

Table of Contents



For more details about  devicetree bindings Reference the Below link: Devicetree

Note: The above devicetree node is by default present in the zynqmp.dtsi file


  1. Source the PetaLinux tool.source /opt/petalinux/petalinux-v<petalinux-version>/
  2. Create a Versal template project or bsp project.

    Code Block
    petalinux-create -t project -n zynqmp-dfx  --template versal

    Code Block
    petalinux-create -t project -s <bsp path> -n zynqmp-dfx

  3. Go to the project

    Code Block
    cd zynqmp-dfx

  4. Configure the project with static.xsa/base.xsa

    Code Block
    petalinux-config --get-hw-description <base.xsa/static.xsa>

  5. Enable FPGA manager using the following command

    Code Block
    petalinux-config -> FPGA MANAGER

  6. Create the static/base application using the following command from static/base xsa

    Code Block
    petalinux-create -t apps --template fpgamanager_dtg -n <static-app> --enable --srcuri "<static xsa>"

    The previous command creates and packages the static dtbo and pdi files into the rootfs (/lib/firmware/xilinx/) using fpgamanager_dtg template.

  7. Create the partial application to configure the partial region using the rm xsa in the following command. You should point static pl app name as --static-pn command line option to define the relation between base and partial.

    Code Block
    petalinux-create -t apps --template fpgamanager_dtg_dfx -n <rm-app> --enable --srcuri <rm.xsa>" --static-pn <static-app>

    This command generates and packages the rm dtbo, pdi files into the rootfs (/lib/firmware/xilinx/<static-app>/<rm-app>).

  8. Execute

    Code Block

    The command generates the rootfs containing both static and rprm dtbos, and respective pdi files as mentioned in the step 5 and step 6.

    Once the base boot images ready with the previous step, if you want to build only DFX apps, use the commands mentioned in step 8.

  9. Execute the following command:

    Code Block
    petalinux-build -c <static-app>
    petalinux-build -c <rm-app>
    in below path you will see with the below names.
    in <TMPDIR>/deploy/rpm you will see <static-app>.rpm and <rm-app>.rpm

    For more details relevant to the above steps refer to this link: Petalinux-DFX-Support

Once the build is complete, binaries are available at images/linux directory.     

  •  Boot the hardware with newly built images
    • Directory /lib/firmware in the rootfs contains the Bitstreams and dtbo files  


Code Block
$ bitbake petalinux-image-minimal

Once the build is complete, binaries are available at ${DEPLOY_DIR_IMAGE} (${TMPDIR}/deploy/images/${MACHINE}/) directory            

      3. Boot the hardware with newly built images


Typical topology: FPGA has the base FPGA Region(static) with two PR/DFx regions (Each PR region has two RMs).  The relevant files can be looked as below.

-- xilinx
    `-- static
        |-- static.dtbo
        |-- static.bin
| `-- PR0-RM0
        | |-- pr0-rm0.dtsi | |-- pr0-rm0.dtbo | |-- pr0-rm0.bin
       | `-- PR0-RM1
| |-- pr0-rm1.dtsi
| |-- pr0-rm1.dtbo
| |-- pr0-rm1.bin
| `-- PR1-RM0
| |-- pr1-rm0.dtsi
| |-- pr1-rm0.dtbo
| |-- pr1-rm0.bin
| `-- PR0-RM1
| |-- pr1-rm1.dtsi
| |-- pr1-rm1.dtbo
| |-- pr1-rm1.bin


Code Block
root@xilinx-zcu102-2018_3:~# fpgautil -r readbackdata -t 1
root@xilinx-zcu102-2018_3:~# hexdump readbackdata.bin > data.txt
Verification of Read-back Data
  • To verify the readback data stream, compare it to the RBD golden readback file and masking readback bits with the MSD file. This approach is simple because there is a 1:1 correspondence between the start of the readback data stream and the start of the RBD and MSD files, making the task of aligning readback, mask, and expected data easier.

  • The RBD and MSD files contain an ASCII representation of the readback and mask data along with a file header that lists the file name, etc. This header information should be ignored or deleted. The ASCII 1s and 0s in the RBD and MSD files correspond to the binary readback data from the device.

  • For generating RBD and MSD refer UG908 (Vivado Design Suite User Guide)

    By compiling the below utility(verify_readback.c file) user can verify the read back contents.
    Source code: verify_readback


Steps for programming the Full Bitstream 

Set flags for Full Bitstream

  • echo 0 > /sys/class/fpga_manager/fpga0/flags


Steps for programming the Partial Bitstream

Set flags for Partial Bitstream

  • echo 1 > /sys/class/fpga_manager/fpga0/flags

Load the Bitstream Partial Bitstream

  • mkdir -p /lib/firmware

  • cp /media/partail_wrapper.bin /lib/firmware/

  • echo partail_wrapper.bin  > /sys/class/fpga_manager/fpga0/firmware


Steps for Readback of Configuration Registers

Set flags for readback type


Steps for Readback of Configuration DataFrames 

Set flags for readback type


Refer this link: libdfx - Linux User Space Solution for FPGA Programming

Mainline Status

The current driver availble in the xilinx linux git is in sync with the open source 6.6 kernel driver except for the following

  • Encrypted and Authenticated Full/Partial Bitstream loading
  • Readback of Configuration Registers
  • Readback of Bitstream(Configuration Data)
  • Use the scatterlist interface

Release history


  • FPGA Manager framework upgraded to 6.6v


  • Revert "fpga: zynqmp: Initialized variables before using it"


  • FPGA Manager framework upgraded to 6.1v


  • FPGA Manager framework upgraded to 5.10v



  • fpga: zynqmp: Use the scatterlist interface
  • fpga: zynqmp: Initialized variables before using it
  • fpga: zynqmp: Fix incorrect variables type


  • 4823227 fpga: zynqmp: Use the scatterlist interface
  • aac8be7 fpga: zynqmp: Initialized variables before using it
  • 2899bc8 fpga: zynqmp: Fix incorrect variables type


  • None



  • fpga: zynqmp-fpga: Adds status interface


  • 8e85861 fpga: zynqmp-fpga: Adds status interface



  • fpga: Fix bitstream typo error
  • Merge tag 'v4.19' into master
  • fpga: ZynqMP: Adds support for Authentication of bitstreams usning User-key
  • drivers: xilinx: Reorganize firmware driver for zynqmp
  • drivers: Defer probe if firmware is not ready
  • fpga: zynqmp: Revert Authentication of bitstreams using User-key changes
  • fpga: zynqmp: Use SPDX license header


  • Added support for vivado generated bit and bin file loading
  • Added support for PL configuration readback 
  • Added support for clock framework 


  • daca3d fpga: zynqmp: Adds support to load vivado generated .bit and .bin files
  • bd1f10  fpga: zynqmp-fpga: Add support for pl configuration readback
  • 097ea7 fpga: zynqmp-fpga: Add support for clock framework 


  • Added Support for Partial Reconfiguration