Zynq UltraScale＋ MPSoC Power Advantage Tool part 6 - Building and
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Zynq UltraScale+ MPSoC Power Advantage Tool part 6 - Building and Running the R5 Design From Sources
It is sometimes helpful to have an example of power management. The Power Advantage Tool R5 code has power management API calls, as well as a useful API interface to the MSP430. This section describes how to build and run the Power Advantage Tool R5 code from sources.
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1 R5 Design
1.1 Building the R5 DesignThe steps to rebuild the R5 design from sources are as follows:
- Install Vivado and SDK as described here.
- Windows > All Programs > Xilinx Design Tools > SDK 2016.2 > Workspace: C:\zynqus\pwr\sw > Project > Build All
1.2 Running the R5 Design from the JTAG DebuggerThe steps to run the R5 design from the JTAG debugger are as follows:
- Plug Micro USB cable in to USB JTAG Port J2.
- Set the Boot Mode Switch (SW6) 1-4 On-On-On-On (JTAG Boot) and reboot the ZCU102.
- Windows > All Programs > Xilinx Design Tools > SDK 2016.2 > Workspace: C:\zynqus\pwr\sw > Right Click r5 > Debug As > Launch on Hardware (System Debugger)
- Note: If you changed the PL design, and now the R5 debugger does not work, please see the Note in the previous PL page, section 1.1.
1.3 Running the R5 Design from SD ImageThe steps to run the R5 design from SD Image are as follows:
- After Building the R5 Design in 1.1, Build an SD card (Standalone is the simplest) and run as described here.
For additional information, please refer to Power Advantage Tool R5 Theory of Operation.pdf