This page This page gives an overview of the Zynq Ultrascale+ MPSoC Clock framework available at drivers/clk/zynqmp/. For CCF to work, PMUFW should be downloaded.
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- Recommend to reserve VPLL for dp_video_ref if DP video is used AR - AR-69345
Kernel Configuration
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| theme | Midnight |
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- used AR - AR-69345
Kernel Configuration
The following config options should be enabled in order to build the ccf driver
CONFIG_COMMON_CLK_ZYNQMP
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Symbol: COMMON_CLK_ZYNQMP [=y] │ │ Type : boolean │ │ Type : boolean │ │ Prompt: Support for Xilinx ZynqMP Ultrascale+ clock controllers │ │ Prompt: Support for Xilinx ZynqMP Ultrascale+ clock controllers │ │ Location: │ │ Location: │ │ -> Device Drivers │ │ -> Device Drivers │ │ (1) -> Common Clock Framework │ │ (1) -> Common Clock Framework │ │ Defined at drivers/clk/zynqmp/Kconfig:1 │ │ Defined at drivers/clk/zynqmp/Kconfig:1 │ │ Depends on: COMMON_CLK [=y] &&&& OF [=y] &&&& (ARCH_ZYNQMP [=y] || COMPILE_TEST [=n]) |
Devicetree (for 2018.1 release)
For more details on clock bindings please refer "Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.txt"
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clk: clk { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = │ │ Depends on: COMMON_CLK [=y] &&&& OF [=y] &&&& (ARCH_ZYNQMP [=y] || COMPILE_TEST [=n]) |
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<&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
};
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Devicetree (for 2017.4 and earlier releases)
For more details on clock phy bindings please refer "Documentation/devicetree/bindings/clock/xlnx,zynqmp-clkzynq_mpsoc.txt"
| Code Block | ||||
|---|---|---|---|---|
| clk: clk {
u-boot,dm-pre-reloc;
||||
clkc: clkc@ff5e0020 { #clock-cells = <1>; compatible = "xlnx,zynqmp-clkclkc"; clocks = <&&pss_ref_clk>, clocks = <&<&&video_clk>, <&&pss_alt_ref_clk>, <&&aux_ref_clk>, <&>_crx_ref_clk>; clock-names = "pss_ref_clk>clk", <&"video_clk>clk", <&"pss_alt_ref_clk>clk", <&"aux_ref_clk>clk", <&"gt_crx_ref_clk>clk"; clock-output-names = "iopll", clock-names = "pss_ref_clk"rpll", "apll", "dpll", "vpll", "videoiopll_to_clkfpd", "pssrpll_alt_refto_clkfpd", "auxapll_refto_clklpd", "gtdpll_crxto_ref_clk"; }; |
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clkc: clkc@ff5e0020 { #clock-cells = <1>;lpd", "vpll_to_lpd", "acpu", "acpu_half", "dbf_fpd", "dbf_lpd", "dbg_trace", compatible = "xlnx,zynqmp-clkc"; clocks = <&&pss_ref_clk>, <&&video_clk>, <&&pss_alt_ref_clk>, <&&aux_ref_clk>, <&>_crx_ref_clk>;"dbg_tstmp", "dp_video_ref", "dp_audio_ref", "dp_stc_ref", "gdma_ref", clock-names = "pssdpdma_ref_clk", "videoddr_clkref", "psssata_alt_ref_clk", "auxpcie_ref_clk", "gtgpu_crx_ref_clk";", clock-output-names = "iopllgpu_pp0_ref", "rpllgpu_pp1_ref", "aplltopsw_main", "dplltopsw_lsbus", "vpll", "iopll_to_fpdgtgref0_ref", "rplllpd_to_fpdswitch", "aplllpd_to_lpdlsbus", "dpllusb0_tobus_lpdref", "vpllusb1_tobus_lpdref", "acpu", "acpu_halfusb3_dual_ref", "dbf_fpdusb0", "dbf_lpdusb1", "dbgcpu_tracer5", "dbgcpu_r5_tstmpcore", "dpcsu_video_refspb", "dpcsu_audio_refpll", "dp_stc_refpcap", "gdmaiou_refswitch", "dpdmagem_tsu_ref", "gem_tsu", "ddrgem0_ref", "satagem1_ref", "pciegem2_ref", "gpugem3_ref", "gem0_tx", "gpu_pp0_refgem1_tx", "gem2_tx", "gpu_pp1gem3_tx", "qspi_ref", "topswsdio0_mainref", "topswsdio1_lsbusref", "gtgref0uart0_ref", "lpduart1_switchref", "lpdspi0_lsbusref", "usb0_busspi1_ref", "nand_ref", "usb1_busi2c0_ref", "i2c1_ref", "usb3_dualcan0_ref", "can1_ref", "usb0can0", "usb1can1", "cpudll_r5ref", "cpu_r5_coreadma_ref", "timestamp_ref", "csu_spbams_ref", "pl0", "pl1", "pl2", "csu_pllpl3", "pcapwdt", "iou_switch", "gem_tsu_ref", "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref", "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx", "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref", "uart0_ref", "uart1_ref", "spi0_ref", "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref", "can0_ref", "can1_ref", "can0", "can1", "dll_ref", "adma_ref", "timestamp_ref", "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"; }; |
Test Procedure
The following driver use cases is tested.
Mainly clock enable and disable on following drivers
- i2c
- qspi
- sd card
- nand
- uart
- gem
- gpio
- dma
- sata
- apm
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root@Xilinx-ZCU102-2016_2:~# ethtool -s eth0 speed 1000 duplex full
root@Xilinx-ZCU102-2016_2:~# [ 1168.866072] macb ff0e0000.ethernet
eth0: link down
Received IPI Mask:0x00000001
PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6050C00
Received IPI Mask:0x00000001
PMUFW: PmMmioWrite: (NODE_APU) addr=0xFF5E005C, mask=0xFFFFFFFF, value=0x6010C00
Received IPI Mask:0x00000001
PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6010C00
[ 1170.890303] macb ff0e0000.ethernet eth0: link up (1000/Full)
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root@Xilinx-ZCU102-2016_2:~# ethtool -s eth0 speed 10 duplex full
root@Xilinx-ZCU102-2016_2:~# [ 1192.898072] macb ff0e0000.ethernet
eth0: link down
Received IPI Mask:0x00000001
PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6010C00
Received IPI Mask:0x00000001
PMUFW: PmMmioWrite: (NODE_APU) addr=0xFF5E005C, mask=0xFFFFFFFF, value=0x6320C00
Received IPI Mask:0x00000001
PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6320C00
[ 1195.922279] macb ff0e0000.ethernet eth0: link up (10/Full)
root@Xilinx-ZCU102-2016_2:~# |
Debug
View the Clock configuration summary.
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cat /sys/kernel/debug/clk/clk_summary
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Change log
2016.3
Summary:
- Adds basic clock support for zynqmp.
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- the GEM mux shift values are corrected.
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- The watchdog source is corrected.
- Since for dp to work it changes the parent rate. We do not support dp sharing the parent (VPLL).A warn is added to check for the same.
- Sets the set rate parent for video clocks.
- Fractional mode support is enabled.
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- In some cases the second divisor was was getting saturated resulting in some ethernet failures.this is fixed.
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- Fix the usb mux offset
- Some waning fixes
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- Remove unused variables
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- Move MMIO error to debug from warn
- Use SPDX license
- Replace clock driver with new driver which fetches clock information from firmware
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- clk: zynqmp: Move a warn to debug
- clk: zynqmp: Use SPDX and update author
- clk: zynqmp: Use firmware APIs in clock driver
- clk: zynqmp: Fix reserved parent comparision
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- None
2018.3
- None
2019.1
Summary:
- clk: zynqmp: Extend driver for versal
- clk: zynqmp: fix doc of __zynqmp_clock_get_parents
- clk: zynqmp: Add support for custom type flags
- drivers: Defer probe if firmware is not ready
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- clk: zynqmp: Extend driver for versal
- clk: zynqmp: fix doc of __zynqmp_clock_get_parents
- clk: zynqmp: Add support for custom type flags
- drivers: clk: Update clock driver to handle clock attribute
2019.2
Summary:
- clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
- clk: zynqmp: Recalculate bestdiv for DIV2 clock
- clk: zynqmp: Warn user if clock user are more than allowed
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- clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
- clk: zynqmp: Recalculate bestdiv for DIV2 clock
- clk: zynqmp: Warn user if clock user are more than allowed
2020.1
Summary:
- clk: zynqmp: Fix CLK_FRAC bit index
- clk: zynqmp: Fix missing max_div description in kernel-doc format
- clk: zynqmp: Fix divider2 calculation
- clk: zynqmp: fix memory leak in zynqmp_register_clocks
- drivers: clk: Fix invalid clock name queries
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- clk: zynqmp: Fix CLK_FRAC bit index
- clk: zynqmp: Fix missing max_div description in kernel-doc format
- clk: zynqmp: Fix divider2 calculation
- clk: zynqmp: fix memory leak in zynqmp_register_clocks
- drivers: clk: Fix invalid clock name queries
2020.2
Summary:
- clk: zynqmp: Handle divider specific read only flag
- clk: zynqmp: Use firmware specific common clock flags
- clk: zynqmp: Use firmware specific mux clock flags
- clk: zynqmp: Add missing checking of eemi_ops
- clk: zynqmp: Add a check for NULL pointer
- clk: zynqmp: Make zynqmp_clk_get_max_divisor static
- clk: zynqmp: make bestdiv unsigned
Commits:
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;
}; |
Test Procedure
The following driver use cases is tested.
Mainly clock enable and disable on following drivers
- i2c
- qspi
- sd card
- nand
- uart
- gem
- gpio
- dma
- sata
- apm
Data rate change is tested with gem.
Sample expected log is below
| Code Block | ||
|---|---|---|
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root@Xilinx-ZCU102-2016_2:~# ethtool -s eth0 speed 1000 duplex full
root@Xilinx-ZCU102-2016_2:~# [ 1168.866072] macb ff0e0000.ethernet
eth0: link down
Received IPI Mask:0x00000001
PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6050C00
Received IPI Mask:0x00000001
PMUFW: PmMmioWrite: (NODE_APU) addr=0xFF5E005C, mask=0xFFFFFFFF, value=0x6010C00
Received IPI Mask:0x00000001
PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6010C00
[ 1170.890303] macb ff0e0000.ethernet eth0: link up (1000/Full)
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| Code Block | ||
|---|---|---|
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root@Xilinx-ZCU102-2016_2:~# ethtool -s eth0 speed 10 duplex full
root@Xilinx-ZCU102-2016_2:~# [ 1192.898072] macb ff0e0000.ethernet
eth0: link down
Received IPI Mask:0x00000001
PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6010C00
Received IPI Mask:0x00000001
PMUFW: PmMmioWrite: (NODE_APU) addr=0xFF5E005C, mask=0xFFFFFFFF, value=0x6320C00
Received IPI Mask:0x00000001
PMUFW: PmMmioRead: (NODE_APU) addr=0xFF5E005C, value=0x6320C00
[ 1195.922279] macb ff0e0000.ethernet eth0: link up (10/Full)
root@Xilinx-ZCU102-2016_2:~# |
Debug
View the Clock configuration summary.
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cat /sys/kernel/debug/clk/clk_summary
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Porting to CCF
Porting to CCF
Mainline status
It is not mainlined. Has dependency on pm.c.
Change log
2016.3
Summary:
- Adds basic clock support for zynqmp.
Commits:
clk: zynqmp: Add initial ccf clkc support
clk: zynqmp: add mux changes for zynqmp
f5e303d clk: zynqmp: Add zynqmp divider support
8592671 clk: zynqmp: Add zynqmp ultrascale gate support
ea2cd726 clk: zynqmp: Add the pll driver
4d85a2c clk: zynqmp: Fix GEM mux shift values
2016.4
Summary:
- the GEM mux shift values are corrected.
Commits:
clk: zynqmp: Fix GEM mux shift values
2017.1
Summary:
- The watchdog source is corrected.
- Since for dp to work it changes the parent rate. We do not support dp sharing the parent (VPLL).A warn is added to check for the same.
- Sets the set rate parent for video clocks.
- Fractional mode support is enabled.
Commits:
clk: zynqmp: Fix the watchdog clock source
clk: zynqmp: Warn on vpll multiuser conditionally
pll: zynqmp: Add support for pll set rate
clk: zynqmp: Set the needed flags
clk: zynqmp: clkc: Enable CLK_SET_RATE_PARENT for more clocks
clk: Reset the child count
clk: zynqmp: pll: Enable the fractional mode when needed
clk: zynqmp: Prevent un-necessary rounding off
clk: zynqmp: Enhance the prints
2017.2
Summary:
- In some cases the second divisor was was getting saturated resulting in some ethernet failures.this is fixed.
Commits:
clk: zynqmp: Let the frac be decided on the frac capability
2017.3
Summary:
- Fix the usb mux offset
- Some waning fixes
Commits:
clkc: zynqmp: fix the usb mux
zynqmp: Use new firmware.h instead of pm.h
clk: zynqmp: divider: Fix the warnings
clk: zynqmp: Remove variables set but not used
2017.4
Summary:
- Remove unused variables
Commits:
clk: zynqmp: Remove a unused variable
2018.1
Summary:
- Move MMIO error to debug from warn
- Use SPDX license
- Replace clock driver with new driver which fetches clock information from firmware
Commits:
- clk: zynqmp: Move a warn to debug
- clk: zynqmp: Use SPDX and update author
- clk: zynqmp: Use firmware APIs in clock driver
- clk: zynqmp: Fix reserved parent comparision
2018.2
- None
2018.3
- None
2019.1
Summary:
- clk: zynqmp: Extend driver for versal
- clk: zynqmp: fix doc of __zynqmp_clock_get_parents
- clk: zynqmp: Add support for custom type flags
- drivers: Defer probe if firmware is not ready
Commits:
- clk: zynqmp: Extend driver for versal
- clk: zynqmp: fix doc of __zynqmp_clock_get_parents
- clk: zynqmp: Add support for custom type flags
- drivers: clk: Update clock driver to handle clock attribute
2019.2
Summary:
- clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
- clk: zynqmp: Recalculate bestdiv for DIV2 clock
- clk: zynqmp: Warn user if clock user are more than allowed
Commits:
- clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
- clk: zynqmp: Recalculate bestdiv for DIV2 clock
- clk: zynqmp: Warn user if clock user are more than allowed
2020.1
Summary:
- clk: zynqmp: Fix CLK_FRAC bit index
- clk: zynqmp: Fix missing max_div description in kernel-doc format
- clk: zynqmp: Fix divider2 calculation
- clk: zynqmp: fix memory leak in zynqmp_register_clocks
- drivers: clk: Fix invalid clock name queries
Commits:
- clk: zynqmp: Fix CLK_FRAC bit index
- clk: zynqmp: Fix missing max_div description in kernel-doc format
- clk: zynqmp: Fix divider2 calculation
- clk: zynqmp: fix memory leak in zynqmp_register_clocks
- drivers: clk: Fix invalid clock name queries
2020.2
Summary:
- clk: zynqmp: Handle divider specific read only flag
- clk: zynqmp: Use firmware specific common clock flags
- clk: zynqmp: Use firmware specific mux clock flags
- clk: zynqmp: Add missing checking of eemi_ops
- clk: zynqmp: Add a check for NULL pointer
- clk: zynqmp: Make zynqmp_clk_get_max_divisor static
- clk: zynqmp: make bestdiv unsigned
Commits:
- clk: zynqmp: Handle divider specific read only flag
- clk: zynqmp: Use firmware specific common clock flags
- clk: zynqmp: Use firmware specific mux clock flags
- clk: zynqmp: Add missing checking of eemi_ops
- clk: zynqmp: Add a check for NULL pointer
- clk: zynqmp: Make zynqmp_clk_get_max_divisor static
- clk: zynqmp: make bestdiv unsigned
2021.1
- None
2021.2
Summary:
- clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
- clk: zynqmp: divider: Align max_div description with mainline
- clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
- clk: zynqmp: pll: Remove some dead code
- clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected
- clk: zynqmp: Sync with mainline
Commits:
- clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
- clk: zynqmp: divider: Align max_div description with mainline
- clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
- clk: zynqmp: pll: Remove some dead code
- clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected
- clk: zynqmp: Sync with mainline
2022.1
Summary:
- clk: zynqmp: Use firmware specific common clock flags
- clk: zynqmp: Use firmware specific mux clock flags
- clk: zynqmp: Add missing checking of eemi_ops
- clk: zynqmp: Add a check for NULL pointerdivider clock flags
- clk: zynqmp: Make zynqmp_clk_get_max_divisor staticUse firmware specific mux clock flags
- clk: zynqmp: make bestdiv unsigned
2021.1
- None
2021.2
Summary:
- Handle divider specific read only flag
- clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enableFix kernel doc
- clk: zynqmp: divider: Align max_div description with mainlineFix a memory leak
Commits:
- clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callbackUse firmware specific common clock flags
- clk: zynqmp: pll: Remove some dead codeUse firmware specific divider clock flags
- clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selectedUse firmware specific mux clock flags
- clk: zynqmp: Sync with mainline
Commits:
- clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enableHandle divider specific read only flag
- clk: zynqmp: Fix a memory leak
2022.2
None
2023.1
Summary:
- clk: zynqmp: divider: Align max_div description with mainlinepll: Remove the limit
- clk: zynqmp: move pll: rectify rate rounding in zynqmp_pll_set_mode out of round_rate callback
Commits:
- clk: zynqmp: pll: Remove some dead codethe limit
- clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selectedclk: zynqmp: Sync with mainlinepll: rectify rate rounding in zynqmp_pll_round_rate
2023.2
None
Related Links
- Linux Drivers
- DTG Common clock framework
- 2017.4 or earlier release clock DTSI
View file name zynqmp-clk.dtsi - 2018.1 DTSI
View file name zynqmp-clk-ccf.dtsi
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