Introduction
The AXI Quad Serial Peripheral Interface connects the AXI4 interface to those SPI slave devices which are supporting the Dual or Quad SPI protocol along with Standard SPI protocol instruction set.
Configuration
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CONFIG_SPI=y
CONFIG_DM_SPI=y |
Device tree
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//Reference node for xilinx-spi for vcu118
axi_quad_spi@44a00000 {
bits-per-word = <8>;
compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a";
fifo-size = <256>;
num-cs = <0x2>;
reg = <0x44a00000 0x10000>;
xlnx,spi-mode = <2>;
}; |
Test procedure
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Zynq>U-Boot> sf probe
SF: Deteced s25fl064l with page size 256 Bytes, erase size 64 KiB, total 8 MiB
Zynq>U-Boot> sf erase 0 100000
SF: 1048576 bytes @ 0x0 Erased: OK
Zynq>U-Boot> mw.b 100000 ab 100000
Zynq>U-Boot> sf write 100000 0 100000
device 0 offset 0x0, size 0x100000
SF: 1048576 bytes @ 0x0 Written: OK
Zynq>U-Boot> sf read 200000 0 100000
device 0 offset 0x0, size 0x100000
SF: 1048576 bytes @ 0x0 Read: OK
Zynq>U-Boot> cmp.b 100000 200000 100000
Total of 1048576 byte(s) were the same |
Features
- Configurable SPI modes:
- Standard SPI mode
- Dual SPI mode
- Quad SPI mode
- Programmable SPI clock phase and polarity
- Configurable FIFO depth (16 or 256 element deep in Dual/Quad/Standard SPI mode)
- Configurable Slave Memories in dual and quad modes
