Versions Compared

Old Version 12

changes.mady.by.user Sam Kemp

Saved on

compared with

New Version 13

changes.mady.by.user Lakshmi Prasanna Eachuri

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

*This page contains info for Frame buffer Read IP too as there is a single driver for both Frame buffer Read and Write IP.

Table of Contents

Table of Contents
maxLevel1

Introduction

The purpose of this page is to describe the the Xilinx Framebuffer Write / Read DMA driver. Video Framebuffer Write / Read IP cores are designed for video applications requiring frame buffers and is designed for high-bandwidth access between the AXI4-Stream video interface and the AXI4-interface.This supports reading and writing a variety of video formats (RGB, YUV 4:4:4, YUV 4:2:2, YUV 4:2:0, Luma only and RGB/BGR/YUV with alpha (only for Read)). The data is packed/unpacked based on the video format. Planar and semi-planar memory formats are available for YUV 4:2:2 and YUV 4:2:0. The memory video format, stride, and frame buffer address are run time programmable. The driver is present in the Xilinx Linux-xlnx github at -  https://github.com/Xilinx/linux-xlnx/blob/master/drivers/dma/xilinx/xilinx_frmbuf.c

...

  • AR68765 - LogiCORE Video Frame Buffer Write - Release Notes and Known Issues for the Vivado 2017.1 tool and later versions

Change Log

2023.1

  • Summary
    • No changes

2022.2

  • Summary
    • No changes

2022.1

  • Summary
    • No changes

2021.2

...

2020.2

2020.1

  • Summary
    • Add support 8 ppc
  • Commits
    • bb91ad8 dmaengine: xilinx: frmbuf: Add support for 8 ppc

2019.2

  • Summary
    • Add support for low latency capture
  • Commits
    • 107831e v4l: xilinx: dma: Use early callback mode for low latency capture
    • 9308da3 Revert "Revert "dma: xilinx: Release buffers before DMA transfer""
    • 4036801 Revert "dma: xilinx: Release buffers before DMA transfer"

...