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The example design covers both bare-metal and Linux use cases and is based on the Answer Record 69446.ware coherence to simplify the system software design such as for user space DMA implementations.

Hardware Block Design

The example design implements two AXI CDMA IPs to perform data transfer through S_AXI_HPC0_FPD and S_AXI_LPD respectively. Additionally an AXI GPIO IP is added to control at runtime the wcache[3:0]/arcache[3:0] and awprot[2:0]/arprot[2:0] bits for both interfaces.

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