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• pl.dtsi: This is a file where all the memory mapped peripheral logic(PL) IP nodes will be available.
• pcw.dtsi: This is a file where the dynamic properties where the PS peripheral needs.
• system-top.dts: This is a file where it contains the memory information, early console and the boot arguments.
• zynqmp.dtsi: This file contains all the PS peripheral information and also the cpu info.
• zynqmp-clk-ccf.dtsi: This file contains all the clock information for the peripheral IPs.
• pl-partial-<RPRM>.dtsi: This is a file where all the memory mapped IP nodes for dynamic function exchange designs(DFX).
• pl-partial-custom-<RPRM>.dtsi: This is a file where we can customize the dfx ip nodes. This will get generated when CONFIG.partial_overlay_custom_dts is set
  • If user issues %xsct set_property CONFIG.partial_overlay_custom_dts "pl-partial-final.dts" command then pl-partial-<RPRM>.dtsi and pl-partial-custom-<RPRM>.dtsi will get created and included in pl-partial-final<RPRM>.dts
  • user should do his changes in pl-partial-custom-<RPRM>.dtsi. With this user can create pl-partial-<rprm>.dtbo or pl-partial-final<RPRM>.dtbo based on his requirements.
• pl-custom.dtsi: This will get generated only when CONFIG.overlay_custom_dts is set. This flag is useful when user want to customize pl.dtsi nodes with user changes when using overlays.
  • If user issues %xsct set_property CONFIG.overlay_custom_dts "pl-final.dts" command then pl.dtsi and pl-custom.dtsi will get created and included in pl-final.dts
  • user should do his changes in pl-custom.dtsi. With this user can create pl.dtbo or pl-final.dtbo based on his requirements.

Apart from these files, based on the board it will generate one more board.dtsi file under the same output directory dt/.  For example, if board is zcu111-reva then it generates dt/zcu111-reva.dtsi.

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           Reference node can be found at https://github.com/Xilinx/device-tree-xlnx/blob/xlnx_rel_v2022.2/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-revb.dtsi#L54-L74

New Features:

• Multi concat block support added
• Added DPU IP support
• Replaced the hardcoded values with the macros for reset and power.
• Added dma channels for axi_mcdma IP support in DTG.
• Generate the memory node for each axi_noc IP for Versal
• Added dfx support in DTG
• generating the aie clock node for versal designs if they have aie ip.
• For aie node you can find the detailed doc in below
• https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/soc/xilinx/xlnx%2Cai-engine.yaml

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convert them into dtbo files using the compiling steps.

Note: DTG will generate the dtsi files for rp-rm.xsa only if it has any memory mapped PL IPs.

How to generate full PL soc boot flow (only for versal)

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xsct % bsp config dt_overlay true

xsct % bsp config partial_overlay_custom_dts "pl-partial-final"

xsct % platform generate

How to enable DT OVERLAY from DTG

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Using HSI commands
1.Clone the device tree repo
https://github.com/Xilinx/device-tree-xlnx
2) Go to the prompt
% hsi
hsi v2017.3 (64-bit)SW Build 2018833 on Wed Oct 4 19:58:07 MDT 2017
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
3)
hsi% open_hw_design system.hdf
4)
hsi% set_repo_path device-tree-xlnx
5)
hsi% create_sw_design -proc psu_cortexa53_0 sd22 -os device_tree
6)
hsi% set_property CONFIG.dt_overlay true [get_os]
7)
hsi% generate_target -dir dt/
hsi% ls dt/
pcw.dtsi pl.dtsi sd22.mss system-top.dts zynqmp-clk-ccf.dtsi zynqmp.dtsi

Using XSCT (From 2019.2 release no hsi support)

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3) hsi open_hw_design system.xsa

4) hsi set_repo_path /home/vabbarap/workspace/sync_dt_tip/dt_15_12_2019 (DTG repo path)

5) hsi create_sw_design -proc psu_cortexa53_0 sd22 -os device_tree 

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