0This page gives an overview of axi traffic generator driver which is available as part of the Xilinx Vivado and SDK distribution.
Table of Contents
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Introduction
This page gives an overview of axi traffic generator driver which is available as part of the Xilinx Vivado and SDK distribution.
The Xilinx® LogiCORE™ IP AXI traffic generator core is a soft Xilinx IP core for
Use with the Xilinx Vivado® Design Suite.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
|---|---|---|
| trafgen | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/trafgen | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/trafgen |
| Info |
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Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/trafgen |
The driver source code is organized into different folders. The table below shows the trafgen driver source organization.
| Directory | Description |
|---|---|
doc | Provides the API and data structure details |
data | Driver .tcl , .mdd and .yaml files |
examples | Example applications that show how to use the driver features |
| src | Driver source files, make and cmakelists file |
Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow
.The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.
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