Page Comparison

In 2018.2 version of design the data was captured sequentially for all the ADC based on the GUI request that itself came sequentially. In the current version (2018.3) data is simultaneously captured for all the 8-ADC channels and provided to GUI sequentially. This now enables the user to simultaneously capture very large sample sizes by making use of large DDR storage.The performance numbers related to DAC/ADC is published on Performance Tables Appendix A Performance Table (of the ZCU111 RFSoC RF Data Converter Evaluation Tool Getting Started Guide).

Clock and Control Changes

The design is clocked with the respective DAC and ADC clocks. There is no usage of PL Clock/SysRef clock in non MTS Mode. Hence the Clock Muxes (BUFGMUXs) have been removed from the design. The channels are clocked using clocks derived from their respective tiles and not from a common source as is the case in MTS design. This design has individual channel start/trigger signals and the common channel start/trigger signal required for MTS is removed. Hence the corresponding GPIO is also removed. The updated design constraint file is updated as a part of the Non-MTS design example design package.

The following is the block diagram of the Non MTS design (DAC side),Corresponding changes are there on ADC side also.

For DAC