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            xadc->clk = devm_clk_get(&&pdev->dev, NULL);
            if (IS_ERR(xadc->clk)) {
                        ret = PTR_ERR(xadc->clk);
                        goto err_free_samplerate_trigger;
            }
            clk_prepare_enable(xadc->clk);

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max3109@0 {
    compatible = "maxim,max3109";
    reg = <0>;
    clocks = <&&osc 0>;
    clock-names = "osc";
};

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Interrupts can be connected direct to an interrupt controller or they can be connected to a GPIO input that can generate an interrupt. The following device tree illustrates the changes required to support this feature. It adds interrupt controller ability to the existing GPIO node and then indicates in the SPI device node that the GPIO node is the interrupt controller.

The interrupts property on the SPI device node uses the same interrupt type (edge, level, etc...) as when connected to an interrupt controller. The interrupt number in the interrupts property is the GPIO pin number on the GPIO controller. For example, on Zynq with the PS GPIO using an MIO for the interrupt, the interrupt number starts at 0 which corresponds to GPIO pin 0 and MIO0. This GPIO pin number is not the same as the GPIO pin numbers see in /sys/class/gpio as those seem to be a virtualized pin number and can be a bigger number as the base.

&&gpio0 {
        #interrupt-cells = <2>;
        interrupt-controller;
};
 
&&spi1  {
 
        adxl345 {
                compatible = "adi,adxl34x";
                reg = <1>;
                spi-max-frequency = <1000000>;
                spi-cpha;
                spi-cpol;
                interrupt-parent = <&&gpio0>;
                interrupts = < 0 4 >;
        };
};

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