Table of Contents

Introduction

The Xilinx LogiCORE IP Zynq UltraScale+ RFSoC RF Data Converter IP core provides a configurable wrapper to allow the RF DAC and RF ADC blocks to be used in IP Integrator designs. Multiple tiles are available on each RFSoC and each tile can have a number of data converters (analog-to-digital (ADC) and digital-to-analog (DAC)). The RF ADCs can sample input frequencies up to 4 GHz at 4 GSPS with excellent noise spectral density. The RF DACs generate output carrier frequencies up to 4 GHz using the 2nd Nyquist zone with excellent noise spectral density at an update rate of 6.4 GSPS. The RF data converters also include power efficient digital down-converters (DDCs) and digital up-converters (DUCs) that include programmable interpolation and decimation, NCO and complex mixer. The DDCs and DUCs can also support dual-band operation.


Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/rfdc

Driver source code is organized into different folders. Below diagram shows the rfdc driver source organization
rfdc
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files

RF-ADC Features

• Tile configuration
  • Four RF-ADCs and one PLL per tile
  • 12-bit RF-ADC resolution, with 16-bit digital signal processing datapath
  • Implemented as either four channels of 2 GSPS, or two channels of 4 GSPS (device dependent).
• Decimation filters
  
  • 1x (bypass filter), 2x, 4x, 8x
  • 80% of Nyquist bandwidth, 89 dB stop-band attenuation.
• Digital Complex Mixers
  • Full complex mixers support real or I/Q inputs from the ADCs
  • 48-bit Numeric Controlled Oscillator (NCO) per RF-ADC
  • Fixed Fs/4, Fs/2 low power frequency mixing mode, where Fs is the sample frequency
  • I/Q and real input signals supported.
• Single/multi-band flexibility
  • 2x bands per 2 GSPS RF-ADC pair
  • Can be configured for real or I/Q inputs.
•  Full bandwidth of the RF-ADC at 4 GSPS can be accessed in bypass mode.
• Input signal amplitude threshold: Two programmable threshold flags per RF-ADC
• Built-in digital correction for external analog quadrature modulators:
  
  • Supports gain, phase, and offset correction for and I/Q input pair (two RF-ADCs).
• SYSREF input signal for multi-channel synchronization.
• Flexible AXI4-Stream interface supports a wide range of programmable logic clock rates and converter sample rates.
• Per tile current-mode logic (CML) clock input buffer with on-chip calibrated 100 Ù termination; supplies the RF-ADC sampling clocks or provides a reference clock for the on-chip PLL.
• Dedicated high-speed, high-performance, differential input buffer per RF-ADC with on-chip calibrated 100 Ù termination (on-die termination).
• Output common mode reference voltage for DC coupling RF-ADC inputs

RF-DAC Features

• Tile configuration
  
  • Four RF-DACs and one PLL per tile
  • 14-bit RF-DAC resolution with 16-bit digital signal processing path
  • Sampling speed 6.4 GSPS per RF-DAC
  • 4 GHz full power output bandwidth
• Interpolation
  
  • 1x (bypass filter), 2x, 4x, 8x
  • 80% pass band, 89 dB stop band attenuation
• Digital Complex Mixers
  
  • Full complex mixers support real or I/Q output signals to the DACs
  • 48-bit NCO per RF-DAC
  • Fixed Fs/4, Fs/2 low-power frequency mixing mode
  • Supports mixed mode RF-DAC functionality which maximizes RF-DAC power in the second Nyquist zone
• Single/multi-band flexibility
  
  • 2x bands per RF-DAC pair
  • Can be configured for real or I/Q outputs
• Full bandwidth in bypass mode
• Digital Correction for external analog quadrature modulators:
  
  • Supports gain, phase, and offset correction for an I/Q output pair (2 RF-DACs)
• sinx/x correction for first Nyquist zone
• External input signal (SYSREF) for multi-channel synchronization of data converter channels.
• Per tile current-mode logic (CML) clock input buffer with on-chip calibrated 100 Ω termination; supplies the RF-DAC sampling clocks or provides a reference clock for the on-chip PLL.
• Supports 20 mA or 32 mA output power mode
  
  Note: Multiband and Multi-tile sync features are not supported by software for 2017.3
  
  

Test Cases

• xrfdc_intr_example.c –

For the RFSoC Data Converter, the interrupts are mostly used for error reporting.
The interrupts do not do any data processing. Since they don’t do any data processing, interrupts are invoked in rare conditions.
The example here attempts to demonstrate users how an error interrupt can be generated. Also once generated how does the processing happen. Upon an interrupt, the control reaches to ScuGIC interrupt handler. From there the control is transferred to the libmetal isr handling which then calls the driver interrupt handler. Users are expected to register their callbacks with the driver interrupt framework.
The actual interrupt handling is expected to happen in the user provided callback.
This example generates ADC fabric interrupts by writing some incorrect fabric data rate based on the read/write clocks.

• xrfdc_selftest_example.c

This example does some writes to the hardware to do some sanity checks and does a reset to restore the original settings

• xrfdc_read_write_example.c

This example uses multiple driver "set" APIs to configure the targeted AMS block. Subsequently it uses "get" APIs to read back the configurations to ensure that the desired configurations are applied.
For DAC it sets the following configurations:
MixerSettings, QMCSettings, Write Fabricrate, Decoder mode, Output Current and Coarse Delay.
For ADC it sets the following configurations:
MixerSettings, QMCSettings, Read Fabricrate and Threshold Settings.
This example shows how to change the configurations for ADC and DAC using driver functions.

• xrfdc_mts_example.c

This example test the Multi-Tile Sync feature and shows how to use the MTS APIs.

Changelog