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Below is a list of available example designs showcasing particular IP, Silicon features, or tool flows, targeting Versal Adaptive SoC devices.Link: General Versal Example Designs
NOC HBMC GitHub Tutorial that introduces different design aspects for the NoC High Bandwidth Memory Controller (HBMC) by providing step-by-step instructions to create different designs and run simulations.
NOC DDR4 Example design where the CIPS is connected to the two DDR4 interfaces (1x72-bit) through the NoC with two integrated DDR4 memory controllers (DDRMCs). The design uses an Inter-NoC Interface (INI) to connect one of the DDRMCs to the CIPS. AXI NoC 0 and AXI NoC 1 each contain four INI ports and one integrated DDRMC.
Linux Boot from HBM
The below page details the steps needed to enable HBM support in the VHK158 to allow Linux to boot from HBM.
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