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The purpose of this page is to describe the the Xilinx Framebuffer Write / Read DMA driver. Video Framebuffer Write / Read IP cores are designed for video applications requiring frame buffers and is designed for high-bandwidth access between the AXI4-Stream video interface and the AXI4-interface.This supports reading and writing a variety of video formats (RGB, YUV 4:4:4, YUV 4:2:2, YUV 4:2:0, Luma only and RGB/BGR/YUV with alpha (only for Read)). The data is packed/unpacked based on the video format. Planar and semi-planar memory formats are available for YUV 4:2:2 and YUV 4:2:0. The memory video format, stride, and frame buffer address are run time programmable. The driver is present in the Xilinx Linux-xlnx github at -  https://github.com/Xilinx/linux-xlnx/blob/master/drivers/dma/xilinx/xilinx_frmbuf.c