This page covers the generation of devicetree source (DTS) files using Xilinx tools as well as the building/compiling of these source files using standard open-source tools. In particular, use of the Xilinx Devicetree Generator (DTG) will be covered for generating DTS files from a Xilinx hardware project while the devicetree compiler (DTC) will be covered for compiling DTS files into a devicetree binary (DTB). Although the primary use of the DTB is to provide it to the Linux kernel so that Linux can be initialized to specific hardware correctly, the DTB can also be used with QEMU to emulate hardware for both Linux and standalone systems.
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Generally for the SOCs there will be a static dts/dtsi files, but when it comes to the FPGA there can be many complicated designs which the peripheral logic(PL) IPs may vary or might be having different configurations.
For these complicated FPGA designs we require a Device tree generator(DTG) where it can generate the dts/dtsi automatically for those designs.
Once we generate there will be different files available in the output directory, say for example pl.dtsi, pcw.dtsi, system-top.dts, zynqmp.dtsi, zynqmp-clk-ccf.dtsi, pl-partial-*.dtsi(the suffix of rprm will be added and this files will get generated only for partial/dfx xsa files). These files are described below.
- pl.dtsi: This is a file where all the memory mapped peripheral logic(PL) IP nodes will be available.
- pcw.dtsi: This is a file where the dynamic properties where the PS peripheral needs.
- system-top.dts: This is a file where it contains the memory information, early console and the boot arguments.
- zynqmp.dtsi: This file contains all the PS peripheral information and also the cpu info.
- zynqmp-clk-ccf.dtsi: This file contains all the clock information for the peripheral IPs.
- pl-partial-<RPRM>.dtsi: This is a file where all the memory mapped IP nodes for dynamic function exchange designs(DFX).
Apart from these files, based on the board it will generate one more board.dtsi file under the same output directory dt/. For example, if board is zcu111-reva then it generates dt/zcu111-reva.dtsi.
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Using HSI commands
1.Clone the device tree repo
https://github.com/Xilinx/device-tree-xlnx
2) Go to the HSI prompt
[vabbarap@xhdl3763 /proj/xhdsswstaff/vabbarap/Overlay/New_hdf> % hsi
hsi v2017.3 (64-bit)SW Build 2018833 on Wed Oct 4 19:58:07 MDT 2017
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
3)
hsi% open_hw_design system.hdf
4)
hsi% set_repo_path /home/vabbarap/workspace/sync_dt_tip/clk_wiz_15_12_2017 (DTG repo path)
5)
hsi% create_sw_design -proc psu_cortexa53_0 sd22 -os device_tree
6)
hsi% set_property CONFIG.dt_overlay true [get_os]
7)
hsi% generate_target -dir dt/
hsi% ls dt/
pcw.dtsi pl.dtsi sd22.mss system-top.dts zynqmp-clk-ccf.dtsi zynqmp.dtsi
Using XSCT (From 2019.2 release no hsi support)
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3) hsi open_hw_design system.xsa
4) hsi set_repo_path /home/vabbarap/workspace/sync_dt_tip/dt_15_12_2019 (DTG repo path)
5) hsi create_sw_design -proc psu_cortexa53_0 sd22 -os device_tree
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