Feature Matrix Table

The Matrix table for various features are given below.

Overview

As mentioned above,in the 2018.2 version of the design, all the features were the part of a single monolithic design. In the subsequent versions the design has been split into three designs based on the functionality. A detailed information about the three designs can be found from the following pages.

This tutorial contains information about:

• How to setup the ZCU111 evaluation board and run the Evaluation Tool.
• How to build all the Evaluation Tool components based on the provided source files via detailed step-by-step tutorials.
• Performance Numbers

Additional material not covered in this tutorial

• Zynq UltraScale+ ZCU111 RFSoC RF Data Converter TRD user guide, UG1287
  • The UG provides the list of device features, software architecture and hardware architecture.

This document provides the steps to build and run the RFSoC RF Data Converter Evaluation Tool. The design demonstrates the capabilities and performance of the RFdc (RF-ADC and RF-DAC) available in Zynq® UltraScale+™ RFSoC devices. The Evaluation Tool serves as a platform for Xilinx customers to evaluate the Zynq® UltraScale+™ RFSoC features and helps them to accelerate the product design cycle.

The Evaluation Tool consists of a ZCU111 evaluation board and a custom graphical user interface (UI) installed on a Windows host machine. The Evaluation Tool allows user to configure the operation of the RF-ADCs & RF-DACs including the associated clocking system, to perform signal generation and capture using RFDACs & RFADCs and to perform RF metrics computation on signal capture for input test signals.

Xilinx Vivado IPI flow is used to create the hardware design which is partitioned between the processing system (PS), RFDC IP, and programmable logic (PL). Xilinx PetaLinux flow is used to create and integrate the software components, including Linux kernel and drivers.

The system level block diagram of the Evaluation Tool design is shown in the below figure.

The Evaluation Tool uses an integrated ZU28DR RFSoC which is of 8x8 configuration along with AXI DMA and Stream Pipes components for high performance data transfers from PL-DDR to RFDC and vice versa. The Stream Pipes comprises of various AXI4 Stream Infrastructure IPs. The AXI DMA is configured in Scatter- Gather (SG) mode for high performance. The Evaluation Tool also makes use of multiple processing units available inside the PS like Gigabit Ethernet, I2C, and SD Interface. The APU inside PS is configured to run in SMP Linux mode. The main task of the Linux application is to configure and control the RF-ADC& RF-DAC blocks and the flow of data through the streaming pipeline.

A custom developed Windows-based user interface (UI) is provided along with the Evaluation Tool. It can interact with the RFSoC device running on the ZCU111 evaluation board. The UI connects to the Linux application running on RFSoC via a TCP Ethernet interface. Based on the commands received from the UI on the host machine, the Linux application on the RFSoC device performs various operations that are described later in the user guide. As a TCP socket is used to transfer the data over Ethernet, it is possible to run the UI on any machine connected to the network.

The Evaluation Tool can be run in three separate modes:

• Standalone RF-DAC: - In this mode, a pattern can be generated using the UI on the host machine. This pattern is constantly replayed on the selected RF-DAC channel. The output of the RF-DAC can be monitored on a standard external equipment like, Spectrum Analyzer or Oscilloscope.
• Standalone RF-ADC: - In this mode, an analog signal from an external equipment can be connected to the RF-ADC Inputs. The digital output of the RF-ADC can be analyzed on the host machine using UI.
• RF-DAC to RF-ADC Loopback: - In this mode, the output of the RF-DAC is looped back to the input of RF-ADC using a daughter card (HW-RFMC-XM500) and SMA cables. A test pattern is generated on the host PC using UI and is sent to the RFSoC by the Ethernet interface. The received test pattern is stored into PL-DDR memory. The stored pattern is then sent to RF-DAC using AXI DMA and Stream Pipe for conversion to analog signal. The transmitted analog signal is looped back into the RF-ADC for converting the analog signal into a digital signal. Once digitized, it is stored into PL-DDR memory using AXI DMA and Stream Pipe and is sent back to the host by the Ethernet interface for analysis.