Introduction‍

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• Full Bitstream Support 
  • Non Secure Bitstream
  • Encrypted  Bitstream
  • Authenticated Bitstream 
  • Authenticated and Encrypted Bitstream
  • Compressed Bitstream
  • Loading Bitstream using Devicetree overlay 
• Partial Bitstream Support that doesn't require PL drivers 
  • Non Secure Partial Bitstream
  • Encrypted Partial Bitstream 
  • Authenticated Partial Bitstream 
  • Authenticated and Encrypted Partial Bitstream 
• Readback 
  • Configuration Registers Readback
  • Configuration Data Readback 

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Known Issues

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• No tool flow support for Partial Bitstream loading using Devicetree Overlay (DTG, Petalinux and Yocto)
  

        Important AR Links

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for PL Programing

The Xilinx device tree generator (https://www.xilinxgithub.com/Xilinx/device-tree-xlnx) currently lacks automated support /answers/70504.html 

• • Valid for all the releases 

Note 1: The descriptions in subsequent sections refer to use of Device Tree Overlay (DTO) fragments with FPGA manager framework. It has to be noted that the generation of DTO fragments are not supported in 2018.2 and earlier official Xilinx Petalinux releases . If you are using older Petalinux release (earlier to 2018.3 release) please go through the  OSL Flow section for building software images.

Note 2: Usage of FPGA Manager with partial bitstreams is not supported by Xilinx Worldwide Technical Support and is considered an advanced use case.

Note 3: Axi Interrupt controller driver doesn't work as kernel modules/overlay like other device drivers due to the below limitation

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for device tree overlay generation for Partial Reconfiguration / DFX designs

Occasionally, bare-metal applications relying on the XilFPGA library may produce an error getting the DONE status.  See Answer Record 70504 for more details - https://www.xilinx.com/support/answers/70504.html 

Summary Table for Partial Reconfiguration / Dynamic Function Exchange Feature Support

Partial Reconfiguration / Dynamic Function Exchange (DFX) is an advanced feature of Xilinx Zynq UltraScale+ MPSoC devices.  Refer to the table below for details.  For PetaLinux releases prior to 2018.3 or for building Linux system images manually, please refer to the Linux OSL Flow page.

AXI Interrupt Controller Support

The AXI Interrupt Controller device driver currently does not support being used as Linux kernel module (or loaded within a device tree overlay).  The driver uses the IRQCHIP_DECLARE macro in order to register itself with the Linux IRQ subsystem.   By default it uses the follow sequence to invoke the xilinx_intc_of_init() ( callback function):

                           startstart_kernel() –>  → init_IRQ() -->  → irqchip_init() -->  → of_irq_init() --> call-back function( → xilinx_intc_of_init()                   If The Driver was registered using IRQCHIP_DECLARE  callback

When using the driver with the IRQCHIP_DECLARE macro, it must be compiled into the monolithic kernel and so that the callback function will can be properly invoked at kernel boot timestartup.

Kernel Configuration

The following config options has to be enabled in order to use FPGA Manager, Please note that these options are enabled by default  through xilinx_zynqmp_defconfig except for the fpga debugfs option. If user wants to test readback feature they have enable it.

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      4. Use petalinux-build command to build the required images

# petalinux-build 

Once build is complete, binaries are available at images/linux directory            

      5. Boot the hardware with newly built images

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# bitbake core-image-minimal 

Once build is complete, binaries are available at images/linux directory            

      3. Boot the hardware with newly built images

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root@xilinx-zcu102-2018_3:~# fpgautil -r readbackdata -t 1
root@xilinx-zcu102-2018_3:~# hexdump readbackdata.bin > data.txt

Verification of Read-back Data

• To verify the readback data stream, compare it to the RBD golden readback file and masking readback bits with the MSD file. This approach is simple because there is a 1:1 correspondence between the start of the readback data stream and the start of the RBD and MSD files, making the task of aligning readback, mask, and expected data easier.

• The RBD and MSD files contain an ASCII representation of the readback and mask data along with a file header that lists the file name, etc. This header information should be ignored or deleted. The ASCII 1s and 0s in the RBD and MSD files correspond to the binary readback data from the device.

• For generating RBD and MSD refer UG908 (Vivado Design Suite User Guide)

  By compiling the below utility(verify_readback.c file) user can verify the read back contents.
  Source code: verify_readback

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Steps for programming the Full Bitstream 

Set flags for Full Bitstream

• echo 0 > /sys/class/fpga_manager/fpga0/flags

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Steps for Readback of Configuration Registers

Set flags for readback type

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Steps for Readback of Configuration DataFrames 

Set flags for readback type

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• rmdir /configfs/device-tree/overlays/partial

Mainline Status

The current driver availble in the xilinx linux git is in sync with the open source 4.19 kernel driver except for the following

• Encrypted and Authenticated Full/Partial Bitstream loading
• Readback of Configuration Registers
• Readback of Bitstream(Configuration Data)

Release history

2020.2

Summary:

• fpga: zynqmp: Use the scatterlist interface
• fpga: zynqmp: Initialized variables before using it
• fpga: zynqmp: Fix incorrect variables type

Commits:

• 4823227 fpga: zynqmp: Use the scatterlist interface
• aac8be7 fpga: zynqmp: Initialized variables before using it
• 2899bc8 fpga: zynqmp: Fix incorrect variables type

2020.1

• None

2019.2

Summary:

• fpga: zynqmp-fpga: Adds status interface

Commits:

• 8e85861 fpga: zynqmp-fpga: Adds status interface

2019.1

Summary:

• fpga: Fix bitstream typo error
• Merge tag 'v4.19' into master
• fpga: ZynqMP: Adds support for Authentication of bitstreams usning User-key
• drivers: xilinx: Reorganize firmware driver for zynqmp
• drivers: Defer probe if firmware is not ready
• fpga: zynqmp: Revert Authentication of bitstreams using User-key changes
• fpga: zynqmp: Use SPDX license header

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• Added support for vivado generated bit and bin file loading
• Added support for PL configuration readback 
• Added support for clock framework 

Commits:

• daca3d fpga: zynqmp: Adds support to load vivado generated .bit and .bin files
• bd1f10  fpga: zynqmp-fpga: Add support for pl configuration readback
• 097ea7 fpga: zynqmp-fpga: Add support for clock framework 

2018.2
Summary:

• Added Support for Partial Reconfiguration

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