This article describes a user friendly way to analyze the performance of the memory controller by reading the APMs within Vitis. Secondly, this article provides an example of utilizing the ATGs to model AXI traffic from the PL. This article targets the Zynq Ultrascale+ MPSoC family, however the principles here may be applied toward other device families.

Overview

Vitis provides a friendly user interface to interact with the integrated AXI Performance Monitors (APMs) in the processing system for Zynq UltraScale+ MPSoC. This interface enables a user to either attach to a running target or to load and run software via JTAG while analyzing the performance of the DDR Memory Controller ports. The memory controller contains 6 separate ports highlighted in the illustration below.

After analyzing the six memory controller ports, it is shown that different masters can access the DDR Controller. Below are some of the masters in a system that can require some DDR bandwidth.

Multiple AXI PL Interfaces
High-speed peripherals in the PS
- DMAs
- DisplayPort
PS Processors: APU & RPU
All low speed peripherals

What is not always clear, is precisely how much bandwidth each master is utilizing. That is why a user-friendly method to access the APMs by the Memory Controller is so critical. This article describes how to utilize this feature with Vitis.

The Vitis tools also provide the ability to model traffic from the programmable logic. In order to model traffic for a custom use-case, the AXI Traffic Generators can be connected to the PL-PS ports shown in the illustration below. The Vitis tools provide an easy to use configuration window to set up the AXI Traffic Generator to help analyze memory performance. This article will also describe how this is done.

AXI Performance Monitors

The APMs in the PS are the same APMs provided in the Vivado IP Catalog. PG037 can be used to look over the programming model to read the performance metrics in a user application. However, the Vitis tools enable a user to access the APMs without much knowledge of the programming model and it does so over JTAG.

One limitation with the APMs at the DDR is that a user can only look at one of the DDR Memory controller ports at a time. This is due to the way the APMs are connected to the ports within the PS. There is really only 1 APM on all of the DDR Memory Controller ports and there is an independent slot for each memory controller port to analyze it. This means all the memory controller ports can be analyzed, but not at the same time. A common way to workaround this limitation is to run through equivalent sequences and cycle through the slots to view the impact of performance on each slot.

How to View APM Metrics with Vitis

In order to view the APM metrics from Vitis, follow the following steps:

Open the Run or Debug Configuration dialog (makes sure you’re connected to a running system via JTAG)
Select to attach to a running target
Edit the Performance Analysis Configuration settings
Configure the APM settings
View the APM Metrics

Below we show to run run through these steps within the Vitis GUI. Open the Run Configuration or Debug Configuration and attach to a target. Whether it’s baremetal software running or Linux running on the ARM subsystem, you can attach to a running target via JTAG to be able to read the APM performance metrics. Below is one way to bring up the Run Configurations.

After run configuration is selected, create a configuration (double click “Single Application Debug”) and setup the Debug Type to “Attach to running target”. Also, select the “Performance Analysis Configuration” to be able to set up which APMs to look at.

Next, select to Configuration APM.

The Performance Analysis APM Configuration is important to set up correctly. The Slots under psu_apm_0 correspond to the Slots to the Memory controller. Their count values align with the count on the S# port number to the Memory Controller from figure from the TRM. Refer to the figure below.

After deciding on a slot to analyze, it is time to attach to the running target to look at the metrics. If a baremetal application is to be analyzed, the application can be run, or attached to. For Linux, it is simplest to attach to a running target via JTAG to monitor the performance. The following relevant tabs will appear in the Performance Analysis perspective.

For metrics on each processor, reference the PS Performance metrics. The graph provides a representation of the utilization of each processor to help determine how fully utilized it is. This tab is not utilizing the APMs, but it can be helpful to view the Performance Monitor Unit within each A53.

The metrics from the APMs are helpful in determining memory bottlenecks. Latency maximums are recorded through the Counters tab and time-based graphs on read/write data are recorded in the graphs tab. Since all Slots to the Memory Controller cannot be simultaneously read, it is common to have to re-run tests and switching between slots to get an overall picture of the performance. Lastly, a log if provided to look at the

AXI Traffic Generators (ATG)

The AXI Traffic Generator is an IP provided through the Vivado IP catalog. This IP is capable of creating AXI read or write transactions to exercise a system with traffic. A good use case for the ATG is to use it in conjunction with the APMs where the ATGs can mimic a master generating traffic from the PL. Below we will describe just that use case and how it can all be controlled from Vitis.

Creating the PL Design

The PL design is quite simple. We connect an ATG to one of the HP ports driving the PS as shown below.

With the ATG set up accordingly:

Controlling the ATGs from Vitis

The ATGs can be accessed from the same window where the APMs are set up.

Once in the window to configure the ATGs, there are various options to set up the traffic similar to your use case. Take a look below for the options.

Notice that the ATGs are run for a specific amount of time, and then they stop. It is also common to change their interval length as well as the beats per transfer. Create the traffic that mimics your anticipated design in the PL and analyze the results with the APMs.

Conclusion

APMs and ATGs can be easily accessed through the Vitis Configurations window. Vitis provides graphs and charts to help analyze the data acquired from the APMs from a running system.

Xilinx Wiki

Analyzing and Modeling Memory Traffic with Vitis

Table of Contents